Andrew F. Davis 39a8fa70f0 PSCI: Fix logic error to skip cache flushing ... If either USE_COHERENT_MEM or HW_ASSISTED_COHERENCY being true should cause us to not enter the ifdef block, then the logic is not correct here. Posibly bad use of De Morgan's law? Fix this. Signed-off-by: Andrew F. Davis <afd@ti.com>		2018-07-26 14:14:06 -05:00
..
aarch32	Invalidate TLB entries during warm boot	2018-02-27 17:00:41 +00:00
aarch64	Invalidate TLB entries during warm boot	2018-02-27 17:00:41 +00:00
psci_common.c	PSCI: Fix logic error to skip cache flushing	2018-07-26 14:14:06 -05:00
psci_lib.mk	mem_protect: Add mem_protect API	2017-09-25 13:32:20 +01:00
psci_main.c	PSCI: Fix MISRA defects in common and setup code	2018-07-24 09:19:34 +01:00
psci_mem_protect.c	PSCI: Fix MISRA defects in MEM_PROTECT	2018-07-24 09:19:22 +01:00
psci_off.c	PSCI: Fix MISRA defects in ON/OFF/SUSPEND/SYSTEM_OFF	2018-07-24 09:19:04 +01:00
psci_on.c	PSCI: Fix MISRA defects in ON/OFF/SUSPEND/SYSTEM_OFF	2018-07-24 09:19:04 +01:00
psci_private.h	PSCI: Fix MISRA defects in common and setup code	2018-07-24 09:19:34 +01:00
psci_setup.c	PSCI: Fix MISRA defects in common and setup code	2018-07-24 09:19:34 +01:00
psci_stat.c	PSCI: Fix MISRA defects in stat code	2018-07-24 09:19:26 +01:00
psci_suspend.c	PSCI: Fix MISRA defects in ON/OFF/SUSPEND/SYSTEM_OFF	2018-07-24 09:19:04 +01:00
psci_system_off.c	PSCI: Fix MISRA defects in ON/OFF/SUSPEND/SYSTEM_OFF	2018-07-24 09:19:04 +01:00