386 lines
12 KiB
C
386 lines
12 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <desc_image_load.h>
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#include <optee_utils.h>
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#include <libfdt.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <string.h>
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#include <utils.h>
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#include "qemu_private.h"
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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#if !LOAD_IMAGE_V2
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL3-1, e.g. while passing control to it from BL2, bl31_params
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* and other platform specific params
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******************************************************************************/
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typedef struct bl2_to_bl31_params_mem {
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bl31_params_t bl31_params;
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image_info_t bl31_image_info;
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image_info_t bl32_image_info;
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image_info_t bl33_image_info;
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entry_point_info_t bl33_ep_info;
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entry_point_info_t bl32_ep_info;
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entry_point_info_t bl31_ep_info;
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} bl2_to_bl31_params_mem_t;
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static bl2_to_bl31_params_mem_t bl31_params_mem;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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/*******************************************************************************
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* This function assigns a pointer to the memory that the platform has kept
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* aside to pass platform specific and trusted firmware related information
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* to BL31. This memory is allocated by allocating memory to
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* bl2_to_bl31_params_mem_t structure which is a superset of all the
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* structure whose information is passed to BL31
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* NOTE: This function should be called only once and should be done
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* before generating params to BL31
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******************************************************************************/
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl31_params_t *bl2_to_bl31_params;
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/*
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* Initialise the memory for all the arguments that needs to
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* be passed to BL3-1
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*/
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zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL3-1 related information */
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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/* Fill BL3-2 related information */
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
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VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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/* Fill BL3-3 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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/* BL3-3 expects to receive the primary CPU MPID (through x0) */
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bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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/* Flush the TF params and the TF plat params */
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)&bl31_params_mem,
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sizeof(bl2_to_bl31_params_mem_t));
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}
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/*******************************************************************************
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* This function returns a pointer to the shared memory that the platform
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* has kept to point to entry point information of BL31 to BL2
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******************************************************************************/
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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#if DEBUG
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bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
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#endif
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return &bl31_params_mem.bl31_ep_info;
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}
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#endif /* !LOAD_IMAGE_V2 */
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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/* Initialize the console to provide early debug support */
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console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
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PLAT_QEMU_CONSOLE_BAUDRATE);
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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plat_qemu_io_setup();
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}
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static void security_setup(void)
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{
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/*
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* This is where a TrustZone address space controller and other
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* security related peripherals, would be configured.
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*/
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}
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static void update_dt(void)
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{
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int ret;
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void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
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ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
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if (ret < 0) {
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ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
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return;
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}
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if (dt_add_psci_node(fdt)) {
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ERROR("Failed to add PSCI Device Tree node\n");
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return;
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}
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if (dt_add_psci_cpu_enable_methods(fdt)) {
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ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
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return;
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}
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ret = fdt_pack(fdt);
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if (ret < 0)
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ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
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}
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void bl2_platform_setup(void)
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{
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security_setup();
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update_dt();
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/* TODO Initialize timer */
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}
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#ifdef AARCH32
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#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
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#else
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#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
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#endif
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void bl2_plat_arch_setup(void)
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{
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QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE, BL2_RO_LIMIT,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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static uint32_t qemu_get_spsr_for_bl32_entry(void)
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{
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#ifdef AARCH64
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL3-2 image.
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*/
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return 0;
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#else
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return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS);
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#endif
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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static uint32_t qemu_get_spsr_for_bl33_entry(void)
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{
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uint32_t spsr;
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#ifdef AARCH64
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unsigned int mode;
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/* Figure out what mode we enter the non-secure world in */
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mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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#else
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spsr = SPSR_MODE32(MODE32_svc,
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plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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#endif
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return spsr;
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}
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#if LOAD_IMAGE_V2
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static int qemu_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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#endif
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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#if defined(SPD_opteed)
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/*
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* OP-TEE expect to receive DTB address in x2.
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* This will be copied into x2 by dispatcher.
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*/
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bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
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#else /* case AARCH32_SP_OPTEE */
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bl_mem_params->ep_info.args.arg0 =
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bl_mem_params->ep_info.args.arg1;
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bl_mem_params->ep_info.args.arg1 = 0;
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bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
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bl_mem_params->ep_info.args.arg3 = 0;
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#endif
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#endif
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bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
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break;
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case BL33_IMAGE_ID:
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#ifdef AARCH32_SP_OPTEE
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/* AArch32 only core: OP-TEE expects NSec EP in register LR */
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pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
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assert(pager_mem_params);
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pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
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#endif
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
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break;
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return qemu_bl2_handle_post_image_load(image_id);
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}
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#else /* LOAD_IMAGE_V2 */
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/*******************************************************************************
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* Before calling this function BL3-1 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL3-1 and set SPSR and security state.
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* On ARM standard platforms we only set the security state of the entrypoint
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******************************************************************************/
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void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
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entry_point_info_t *bl31_ep_info)
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{
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SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
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bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL3-2 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL3-2 and set SPSR and security state.
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* On ARM standard platforms we only set the security state of the entrypoint
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******************************************************************************/
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
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}
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/*******************************************************************************
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* Before calling this function BL3-3 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL3-3 and set SPSR and security state.
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* On ARM standard platforms we only set the security state of the entrypoint
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******************************************************************************/
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
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bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL33
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******************************************************************************/
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = NS_DRAM0_BASE;
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bl33_meminfo->total_size = NS_DRAM0_SIZE;
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bl33_meminfo->free_base = NS_DRAM0_BASE;
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bl33_meminfo->free_size = NS_DRAM0_SIZE;
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}
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#endif /* !LOAD_IMAGE_V2 */
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return NS_IMAGE_OFFSET;
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}
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