arm-trusted-firmware/lib/extensions
Andre Przywara b85359296c SPE: Fix feature detection
Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any values greater than 0
indicate the presence of a feature, which is what we are after in
our spe_supported() function.

Change the comparison to include all values greater than 0.

This fixes SPE support in non-secure world on implementations which
include the Scalable Vector Extension (SVE), for instance on Zeus cores.

Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-09-14 18:00:18 +01:00
..
amu TF-A AMU: remove AMU enable info print 2020-08-13 14:26:43 +02:00
mpam TF-A: Fix wrong register read for MPAM extension 2020-05-26 15:39:52 +00:00
pauth TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U 2019-10-03 14:43:55 +01:00
ras Tegra194: add RAS exception handling 2020-06-12 09:43:54 -07:00
spe SPE: Fix feature detection 2020-09-14 18:00:18 +01:00
sve Sanitise includes across codebase 2019-01-04 10:43:17 +00:00