311 lines
11 KiB
C
311 lines
11 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cci400.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform.h>
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#include <xlat_tables.h>
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#include "../fvp_def.h"
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/*******************************************************************************
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* This array holds the characteristics of the differences between the three
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* FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
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* boot at each boot stage by the primary before enabling the MMU (to allow cci
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* configuration) & used thereafter. Each BL will have its own copy to allow
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* independent operation.
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******************************************************************************/
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static unsigned long platform_config[CONFIG_LIMIT];
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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*
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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void enable_mmu_el##_el(void) \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr; \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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write_mair_el##_el(mair); \
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\
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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\
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/* Set TCR bits as well. */ \
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/* Inner & outer WBWA & shareable + T0SZ = 32 */ \
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
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TCR_RGN_INNER_WBA | TCR_T0SZ_4GB; \
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) l1_xlation_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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/* into memory, the TLB invalidation is complete, */ \
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/* and translation register writes are committed */ \
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/* before enabling the MMU */ \
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dsb(); \
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isb(); \
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT; \
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sctlr |= SCTLR_A_BIT | SCTLR_C_BIT; \
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write_sctlr_el##_el(sctlr); \
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\
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/* Ensure the MMU enable takes effect immediately */ \
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isb(); \
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}
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
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DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t fvp_mmap[] = {
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{ TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
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{ FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ FLASH1_BASE, FLASH1_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
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{ VRAM_BASE, VRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
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{ DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ NSRAM_BASE, NSRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
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{ DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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/* 2nd GB as device for now...*/
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{ 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE },
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{ DRAM1_BASE, DRAM1_SIZE, MT_MEMORY | MT_RW | MT_NS },
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{0}
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};
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/*******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void configure_mmu_el##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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unsigned long coh_limit) \
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{ \
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mmap_add_region(total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add_region(coh_start, coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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mmap_add(fvp_mmap); \
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init_xlat_tables(); \
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\
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enable_mmu_el##_el(); \
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}
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/* Define EL1 and EL3 variants of the function initialising the MMU */
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DEFINE_CONFIGURE_MMU_EL(1)
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DEFINE_CONFIGURE_MMU_EL(3)
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/* Simple routine which returns a configuration variable value */
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unsigned long platform_get_cfgvar(unsigned int var_id)
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{
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assert(var_id < CONFIG_LIMIT);
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return platform_config[var_id];
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}
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/*******************************************************************************
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* A single boot loader stack is expected to work on both the Foundation FVP
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* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
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* SYS_ID register provides a mechanism for detecting the differences between
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* these platforms. This information is stored in a per-BL array to allow the
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* code to take the correct path.Per BL platform configuration.
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******************************************************************************/
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int platform_config_setup(void)
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{
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unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
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sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
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rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
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hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK;
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bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK;
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arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK;
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if ((rev != REV_FVP) || (arch != ARCH_MODEL))
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panic();
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/*
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* The build field in the SYS_ID tells which variant of the GIC
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* memory is implemented by the model.
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*/
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switch (bld) {
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case BLD_GIC_VE_MMAP:
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platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
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platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
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platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
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platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
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break;
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case BLD_GIC_A53A57_MMAP:
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platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
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platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
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platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
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platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
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break;
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default:
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assert(0);
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}
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/*
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* The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
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* for the Foundation FVP.
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*/
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switch (hbi) {
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case HBI_FOUNDATION:
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF1] = 1;
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_BASE_MMAP] = 0;
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platform_config[CONFIG_HAS_CCI] = 0;
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platform_config[CONFIG_HAS_TZC] = 0;
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break;
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case HBI_FVP_BASE:
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midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
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if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
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platform_config[CONFIG_CPU_SETUP] = 1;
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else
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platform_config[CONFIG_CPU_SETUP] = 0;
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platform_config[CONFIG_MAX_AFF0] = 4;
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platform_config[CONFIG_MAX_AFF1] = 2;
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platform_config[CONFIG_BASE_MMAP] = 1;
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platform_config[CONFIG_HAS_CCI] = 1;
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platform_config[CONFIG_HAS_TZC] = 1;
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break;
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default:
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assert(0);
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}
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return 0;
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}
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unsigned long plat_get_ns_image_entrypoint(void)
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{
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return NS_IMAGE_OFFSET;
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}
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uint64_t plat_get_syscnt_freq(void)
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{
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uint64_t counter_base_frequency;
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/* Read the frequency from Frequency modes table */
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counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
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/* The first entry of the frequency modes table must not be 0 */
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assert(counter_base_frequency != 0);
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return counter_base_frequency;
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}
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void fvp_cci_setup(void)
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{
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unsigned long cci_setup;
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/*
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* Enable CCI-400 for this cluster. No need
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* for locks as no other cpu is active at the
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* moment
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup)
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cci_enable_coherency(read_mpidr());
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}
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/*******************************************************************************
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* Set SPSR and secure state for BL32 image
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******************************************************************************/
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void fvp_set_bl32_ep_info(entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Set SPSR and secure state for BL33 image
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******************************************************************************/
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void fvp_set_bl33_ep_info(entry_point_info_t *bl33_ep_info)
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{
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unsigned long el_status;
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unsigned int mode;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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if (el_status)
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mode = MODE_EL2;
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else
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mode = MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
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}
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