409 lines
14 KiB
C
409 lines
14 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <gic_v3.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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#include "fvp_def.h"
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#include "fvp_private.h"
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/*******************************************************************************
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* This function does some minimal GICv3 configuration. The Firmware itself does
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* not fully support GICv3 at this time and relies on GICv2 emulation as
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* provided by GICv3. This function allows software (like Linux) in later stages
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* to use full GICv3 features.
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******************************************************************************/
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void gicv3_cpuif_setup(void)
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{
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unsigned int scr_val, val;
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uintptr_t base;
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/*
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* When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
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* bit set. In order to allow interrupts to get routed to the CPU we
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* need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
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* to clear (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val &= ~WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to clear. */
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val = gicr_read_waker(base);
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while (val & WAKER_CA) {
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val = gicr_read_waker(base);
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}
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/*
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* We need to set SCR_EL3.NS in order to see GICv3 non-secure state.
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* Restore SCR_EL3.NS again before exit.
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*/
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scr_val = read_scr();
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write_scr(scr_val | SCR_NS_BIT);
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isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */
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/*
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* By default EL2 and NS-EL1 software should be able to enable GICv3
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* System register access without any configuration at EL3. But it turns
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* out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So
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* we need to set it here again. In order to do that we need to enable
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* register access. We leave it enabled as it should be fine and might
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* prevent problems with later software trying to access GIC System
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* Registers.
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*/
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val = read_icc_sre_el3();
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write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
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val = read_icc_sre_el2();
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write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE);
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write_icc_pmr_el1(GIC_PRI_MASK);
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isb(); /* commite ICC_* changes before setting NS=0 */
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/* Restore SCR_EL3 */
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write_scr(scr_val);
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isb(); /* ensure NS=0 takes effect immediately */
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}
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/*******************************************************************************
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* This function does some minimal GICv3 configuration when cores go
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* down.
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******************************************************************************/
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void gicv3_cpuif_deactivate(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
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* wait for GICR_WAKER.ChildrenAsleep to get set.
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* (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val |= WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to set. */
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val = gicr_read_waker(base);
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while ((val & WAKER_CA) == 0) {
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val = gicr_read_waker(base);
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}
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}
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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void gic_cpuif_setup(unsigned int gicc_base)
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{
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unsigned int val;
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val = gicc_read_iidr(gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. We want to
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* allow default GICv2 behaviour but allow the next stage to
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* enable full gicv3 features.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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gicv3_cpuif_setup();
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}
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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gicc_write_ctlr(gicc_base, val);
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}
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void gic_cpuif_deactivate(unsigned int gicc_base)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(gicc_base);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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val = gicc_read_iidr(gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* RDIST is put to sleep.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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gicv3_cpuif_deactivate();
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}
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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void gic_pcpu_distif_setup(unsigned int gicd_base)
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{
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gicd_write_igroupr(gicd_base, 0, ~0);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6);
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gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6);
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gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7);
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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void gic_distif_setup(unsigned int gicd_base)
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{
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unsigned int ctr, num_ints, ctlr;
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/* Disable the distributor before going further */
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ctlr = gicd_read_ctlr(gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(gicd_base, ctlr);
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/*
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* Mark out non-secure interrupts. Calculate number of
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* IGROUPR registers to consider. Will be equal to the
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* number of IT_LINES
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*/
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num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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num_ints++;
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for (ctr = 0; ctr < num_ints; ctr++)
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gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0);
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/* Configure secure interrupts now */
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gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG);
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gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG,
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platform_get_core_pos(read_mpidr()));
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gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG);
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gic_pcpu_distif_setup(gicd_base);
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gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0);
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}
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void gic_setup(void)
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{
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unsigned int gicd_base, gicc_base;
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gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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gic_cpuif_setup(gicc_base);
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gic_distif_setup(gicd_base);
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}
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/*******************************************************************************
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. The platform knows which interrupt controller type is being used
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* in a particular security state e.g. with an ARM GIC, normal world could use
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* the GICv2 features while the secure world could use GICv3 features and vice
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* versa.
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* This function is exported by the platform to let the interrupt management
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* framework determine for a type of interrupt and security state, which line
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* should be used in the SCR_EL3 to control its routing to EL3. The interrupt
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* line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
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uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
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{
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uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert(security_state == NON_SECURE || security_state == SECURE);
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/*
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* We ignore the security state parameter under the assumption that
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* both normal and secure worlds are using ARM GICv2. This parameter
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* will be used when the secure world starts using GICv3.
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*/
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#if FVP_GIC_ARCH == 2
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return gicv2_interrupt_type_to_line(gicc_base, type);
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#else
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#error "Invalid GIC architecture version specified for FVP port"
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#endif
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}
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#if FVP_GIC_ARCH == 2
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t ic_get_pending_interrupt_type()
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{
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uint32_t id, gicc_base;
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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id = gicc_read_hppir(gicc_base);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (id < 1022)
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return INTR_TYPE_S_EL1;
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if (id == GIC_SPURIOUS_INTERRUPT)
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return INTR_TYPE_INVAL;
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return INTR_TYPE_NS;
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t ic_get_pending_interrupt_id()
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{
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uint32_t id, gicc_base;
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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id = gicc_read_hppir(gicc_base);
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if (id < 1022)
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return id;
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if (id == 1023)
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return INTR_ID_UNAVAILABLE;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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return gicc_read_ahppir(gicc_base);
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending interrupt. It returns the contents of the IAR.
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******************************************************************************/
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uint32_t ic_acknowledge_interrupt()
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{
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return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR));
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}
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/*******************************************************************************
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active interrupt
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******************************************************************************/
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void ic_end_of_interrupt(uint32_t id)
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{
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gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id);
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return;
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1.
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******************************************************************************/
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uint32_t ic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id);
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/* Assume that all secure interrupts are S-EL1 interrupts */
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if (group == GRP0)
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return INTR_TYPE_S_EL1;
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else
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return INTR_TYPE_NS;
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}
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#else
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#error "Invalid GIC architecture version specified for FVP port"
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#endif
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