70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <gicv3.h>
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#include <interrupt_props.h>
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#include <k3_gicv3.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <utils.h>
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/* The GICv3 driver only needs to be initialized in EL3 */
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t k3_interrupt_props[] = {
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PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
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};
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static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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gicv3_driver_data_t k3_gic_data = {
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.interrupt_props = k3_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(k3_interrupt_props),
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.mpidr_to_core_pos = k3_mpidr_to_core_pos,
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};
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void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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k3_gic_data.gicd_base = gicd_base;
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k3_gic_data.gicr_base = gicr_base;
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gicv3_driver_init(&k3_gic_data);
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}
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void k3_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void k3_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void k3_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void k3_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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