99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_DEFAULT_HELPER_MACROS_H
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#define SOC_DEFAULT_HELPER_MACROS_H
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#ifdef NXP_OCRAM_TZPC_ADDR
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#define TZPC_BLOCK_SIZE 0x1000
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#endif
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/* Reset block register offsets */
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#ifdef NXP_RESET_ADDR
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/* Register Offset */
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#define RST_RSTCR_OFFSET 0x0
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#define RST_RSTRQMR1_OFFSET 0x10
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#define RST_RSTRQSR1_OFFSET 0x18
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#define BRR_OFFSET 0x60
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/* helper macros */
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#define RSTRQMR_RPTOE_MASK (1 << 19)
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#endif /* NXP_RESET_ADDR */
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#define PCIeRC_RN_I_NODE_ID_OFFSET 0x8
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#define PoS_CONTROL_REG_OFFSET 0x0
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#define POS_EARLY_WR_COMP_EN 0x20
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#define HNI_POS_EN 0x01
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#define POS_TERMINATE_BARRIERS 0x10
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#define SERIALIZE_DEV_nGnRnE_WRITES 0x200
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#define ENABLE_ERR_SIGNAL_TO_MN 0x4
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#define ENABLE_RESERVE_BIT53 0x400
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#define ENABLE_WUO 0x10
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#define PORT_S0_CTRL_REG_RNI 0x010
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#define PORT_S1_CTRL_REG_RNI 0x110
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#define PORT_S2_CTRL_REG_RNI 0x210
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#define ENABLE_FORCE_RD_QUO 0x20
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#define QOS_SETTING 0x00FF000C
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/* epu register offsets and values */
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#define EPU_EPGCR_OFFSET 0x0
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#define EPU_EPIMCR10_OFFSET 0x128
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#define EPU_EPCTR10_OFFSET 0xa28
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#define EPU_EPCCR10_OFFSET 0x828
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#ifndef EPU_EPCCR10_VAL
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#define EPU_EPCCR10_VAL 0xb2800000
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#endif
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#define EPU_EPIMCR10_VAL 0xba000000
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#define EPU_EPCTR10_VAL 0x0
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#define EPU_EPGCR_VAL (1 << 31)
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#ifdef NXP_CCN_ADDR
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#define NXP_CCN_HN_F_1_ADDR 0x04210000
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#define CCN_HN_F_SAM_NODEID_MASK 0x7f
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#define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200
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#define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210
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#define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220
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#define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00
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#define CCN_HNF_NODE_COUNT 8
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#define CCN_HNF_OFFSET 0x10000
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#define SA_AUX_CTRL_REG_OFFSET 0x500
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#define NUM_HNI_NODE 2
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#define CCN_HNI_MEMORY_MAP_SIZE 0x10000
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#define PCIeRC_RN_I_NODE_ID_OFFSET 0x8
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#define PoS_CONTROL_REG_OFFSET 0x0
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#define POS_EARLY_WR_COMP_EN 0x20
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#define HNI_POS_EN 0x01
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#define POS_TERMINATE_BARRIERS 0x10
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#define SERIALIZE_DEV_nGnRnE_WRITES 0x200
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#define ENABLE_ERR_SIGNAL_TO_MN 0x4
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#define ENABLE_RESERVE_BIT53 0x400
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#define ENABLE_WUO 0x10
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#endif
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/* reset register bit */
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#define RSTRQMR_RPTOE_MASK (1 << 19)
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/* secmon register offsets and bitfields */
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#define SECMON_HPCOMR_OFFSET 0x4
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#define SECMON_HPCOMR_NPSWAEN 0x80000000
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/* Secure-Register-File register offsets and bit masks */
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#ifdef NXP_RST_ADDR
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/* Register Offset */
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#define CORE_HOLD_OFFSET 0x140
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#endif
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#define DCFG_SBEESR2_ADDR 0x00100534
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#define DCFG_MBEESR2_ADDR 0x00100544
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/* SBEESR and MBEESR bit mask */
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#define OCRAM_EESR_MASK 0x00000008
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#endif /* SOC_DEFAULT_HELPER_MACROS_H */
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