176 lines
4.1 KiB
C
176 lines
4.1 KiB
C
/*
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* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#if RCAR_LSI == RCAR_AUTO
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#include "G2M/qos_init_g2m_v10.h"
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#include "G2M/qos_init_g2m_v11.h"
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#include "G2M/qos_init_g2m_v30.h"
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#endif /* RCAR_LSI == RCAR_AUTO */
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#if (RCAR_LSI == RZ_G2M)
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#include "G2M/qos_init_g2m_v10.h"
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#include "G2M/qos_init_g2m_v11.h"
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#include "G2M/qos_init_g2m_v30.h"
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#endif /* RCAR_LSI == RZ_G2M */
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#include "qos_common.h"
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#include "qos_init.h"
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#include "qos_reg.h"
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#include "rcar_def.h"
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#define DRAM_CH_CNT 0x04U
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uint32_t qos_init_ddr_ch;
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uint8_t qos_init_ddr_phyvalid;
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#define PRR_PRODUCT_ERR(reg) \
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{ \
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ERROR("LSI Product ID(PRR=0x%x) QoS " \
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"initialize not supported.\n", reg); \
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panic(); \
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}
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#define PRR_CUT_ERR(reg) \
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{ \
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ERROR("LSI Cut ID(PRR=0x%x) QoS " \
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"initialize not supported.\n", reg); \
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panic(); \
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}
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void rzg_qos_init(void)
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{
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uint32_t reg;
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uint32_t i;
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qos_init_ddr_ch = 0U;
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qos_init_ddr_phyvalid = rzg_get_boardcnf_phyvalid();
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for (i = 0U; i < DRAM_CH_CNT; i++) {
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if ((qos_init_ddr_phyvalid & (1U << i))) {
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qos_init_ddr_ch++;
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}
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}
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reg = mmio_read_32(PRR);
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#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
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switch (reg & PRR_PRODUCT_MASK) {
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case PRR_PRODUCT_M3:
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M)
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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qos_init_g2m_v10();
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break;
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case PRR_PRODUCT_21: /* G2M Cut 13 */
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qos_init_g2m_v11();
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break;
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case PRR_PRODUCT_30: /* G2M Cut 30 */
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default:
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qos_init_g2m_v30();
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break;
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}
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#else /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
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PRR_PRODUCT_ERR(reg);
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#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
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break;
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default:
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PRR_PRODUCT_ERR(reg);
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break;
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}
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#else /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
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#if (RCAR_LSI == RZ_G2M)
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* G2M Cut 10 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_g2m_v10();
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#elif RCAR_LSI_CUT == RCAR_CUT_11
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/* G2M Cut 11 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_g2m_v11();
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#elif RCAR_LSI_CUT == RCAR_CUT_13
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/* G2M Cut 13 */
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if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21)
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!= (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_g2m_v11();
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#else
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/* G2M Cut 30 or later */
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if ((PRR_PRODUCT_M3)
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!= (reg & (PRR_PRODUCT_MASK))) {
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PRR_PRODUCT_ERR(reg);
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}
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qos_init_g2m_v30();
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#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
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#else /* (RCAR_LSI == RZ_G2M) */
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#error "Don't have QoS initialize routine(Unknown chip)."
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#endif /* (RCAR_LSI == RZ_G2M) */
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#endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
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}
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uint32_t get_refperiod(void)
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{
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uint32_t refperiod = QOSWT_WTSET0_CYCLE;
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#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
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uint32_t reg;
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reg = mmio_read_32(PRR);
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switch (reg & PRR_PRODUCT_MASK) {
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M)
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case PRR_PRODUCT_M3:
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switch (reg & PRR_CUT_MASK) {
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case PRR_PRODUCT_10:
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break;
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case PRR_PRODUCT_20: /* G2M Cut 11 */
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case PRR_PRODUCT_21: /* G2M Cut 13 */
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case PRR_PRODUCT_30: /* G2M Cut 30 */
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default:
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refperiod = REFPERIOD_CYCLE;
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break;
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}
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break;
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#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
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default:
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break;
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}
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#elif RCAR_LSI == RZ_G2M
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#if RCAR_LSI_CUT == RCAR_CUT_10
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/* G2M Cut 10 */
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#else /* RCAR_LSI_CUT == RCAR_CUT_10 */
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/* G2M Cut 11|13|30 or later */
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refperiod = REFPERIOD_CYCLE;
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#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
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#endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
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return refperiod;
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}
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void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos,
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unsigned int qos_size, bool dbsc_wren)
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{
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unsigned int i;
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/* Register write enable */
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if (dbsc_wren) {
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mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U);
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}
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for (i = 0; i < qos_size; i++) {
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mmio_write_32(qos[i].reg, qos[i].val);
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}
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/* Register write protect */
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if (dbsc_wren) {
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mmio_write_32(DBSC_DBSYSCNT0, 0x00000000U);
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}
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}
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