Varun Wadekar e0d913c786 Add macros for retention control in Cortex-A53/A57 ... This patch adds macros suitable for programming the Advanced SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic retention control policy in the CPUECTLR_EL1 and L2ECTLR registers. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2015-08-24 21:30:21 +05:30
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aarch64	Remove use of PLATFORM_CACHE_LINE_SIZE	2015-04-27 18:05:06 +01:00
cpus/aarch64	Add macros for retention control in Cortex-A53/A57	2015-08-24 21:30:21 +05:30
bakery_lock.h	Remove the `owner` field in bakery_lock_t data structure	2015-03-27 10:20:32 +00:00
cassert.h	Separate out CASSERT macro into own header	2014-05-06 12:35:02 +01:00
mmio.h	Add mmio utility functions	2015-08-05 19:55:06 +08:00
semihosting.h	Remove variables from .data section	2014-05-06 17:55:38 +01:00
spinlock.h	Always use named structs in header files	2014-05-06 13:57:48 +01:00