63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mce.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#define MISCREG_CPU_RESET_VECTOR 0x2000
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#define MISCREG_AA64_RST_LOW 0x2004
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#define MISCREG_AA64_RST_HIGH 0x2008
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#define CPU_RESET_MODE_AA64 1
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extern void tegra_secure_entrypoint(void);
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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extern void tegra186_cpu_reset_handler(void);
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extern uint64_t __tegra186_smmu_ctx_start;
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#endif
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t addr_low, addr_high;
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base;
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#else
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uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
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#endif
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INFO("Setting up secondary CPU boot\n");
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#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
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memcpy((void *)((uintptr_t)cpu_reset_handler_base),
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(void *)(uintptr_t)tegra186_cpu_reset_handler,
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(uintptr_t)&__tegra186_smmu_ctx_start -
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(uintptr_t)tegra186_cpu_reset_handler);
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#endif
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addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
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addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
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/* write lower 32 bits first, then the upper 11 bits */
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
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addr_high);
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}
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