34 lines
1.0 KiB
C
34 lines
1.0 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_ARES_H__
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#define __CORTEX_ARES_H__
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/* Cortex-ARES MIDR for revision 0 */
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#define CORTEX_ARES_MIDR 0x410fd0c0
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_ARES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
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/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
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#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
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#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
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#define CORTEX_ARES_AMU_NR_COUNTERS U(5)
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#define CORTEX_ARES_AMU_GROUP0_MASK U(0x1f)
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/* Instruction patching registers */
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#define CPUPSELR_EL3 S3_6_C15_C8_0
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#define CPUPCR_EL3 S3_6_C15_C8_1
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#define CPUPOR_EL3 S3_6_C15_C8_2
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#define CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* __CORTEX_ARES_H__ */
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