31 lines
696 B
C
31 lines
696 B
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __DENVER_H__
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#define __DENVER_H__
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/* MIDR values for Denver */
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#define DENVER_MIDR_PN0 U(0x4E0F0000)
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#define DENVER_MIDR_PN1 U(0x4E0F0010)
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#define DENVER_MIDR_PN2 U(0x4E0F0020)
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#define DENVER_MIDR_PN3 U(0x4E0F0030)
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#define DENVER_MIDR_PN4 U(0x4E0F0040)
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/* Implementer code in the MIDR register */
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#define DENVER_IMPL U(0x4E)
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/* CPU state ids - implementation defined */
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#define DENVER_CPU_STATE_POWER_DOWN U(0x3)
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#ifndef __ASSEMBLY__
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/* Disable Dynamic Code Optimisation */
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void denver_disable_dco(void);
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#endif
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#endif /* __DENVER_H__ */
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