317 lines
14 KiB
C
317 lines
14 KiB
C
/*
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* Copyright(C)2022, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_SPM_VCOREFS_H
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#define MT_SPM_VCOREFS_H
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uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
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enum vcorefs_smc_cmd {
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VCOREFS_SMC_CMD_0 = 0U,
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VCOREFS_SMC_CMD_1 = 1U,
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VCOREFS_SMC_CMD_2 = 2U,
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VCOREFS_SMC_CMD_3 = 3U,
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VCOREFS_SMC_CMD_4 = 4U,
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/* check spmfw status */
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VCOREFS_SMC_CMD_5 = 5U,
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/* get spmfw type */
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VCOREFS_SMC_CMD_6 = 6U,
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/* get spm reg status */
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VCOREFS_SMC_CMD_7 = 7U,
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NUM_VCOREFS_SMC_CMD = 8U,
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};
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enum vcorefs_smc_cmd_new {
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VCOREFS_SMC_CMD_INIT = 0U,
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VCOREFS_SMC_CMD_KICK = 1U,
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VCOREFS_SMC_CMD_OPP_TYPE = 2U,
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VCOREFS_SMC_CMD_FW_TYPE = 3U,
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VCOREFS_SMC_CMD_GET_UV = 4U,
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VCOREFS_SMC_CMD_GET_FREQ = 5U,
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VCOREFS_SMC_CMD_GET_NUM_V = 6U,
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VCOREFS_SMC_CMD_GET_NUM_F = 7U,
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VCOREFS_SMC_CMD_FB_ACTION = 8U,
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/*chip specific setting */
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VCOREFS_SMC_CMD_SET_FREQ = 16U,
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VCOREFS_SMC_CMD_SET_EFUSE = 17U,
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VCOREFS_SMC_CMD_GET_EFUSE = 18U,
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VCOREFS_SMC_CMD_DVFS_HOPPING = 19U,
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VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20U,
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};
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enum dvfsrc_channel {
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DVFSRC_CHANNEL_1 = 1U,
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DVFSRC_CHANNEL_2 = 2U,
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DVFSRC_CHANNEL_3 = 3U,
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DVFSRC_CHANNEL_4 = 4U,
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NUM_DVFSRC_CHANNEL = 5U,
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};
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struct reg_config {
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uint32_t offset;
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uint32_t val;
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};
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#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
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#define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
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#define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
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#define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
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#define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
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#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
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#define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
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#define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
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#define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
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#define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
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#define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28)
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#define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C)
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#define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30)
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#define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34)
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#define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38)
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#define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C)
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#define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40)
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#define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44)
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#define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48)
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#define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C)
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#define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50)
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#define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54)
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#define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58)
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#define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C)
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#define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60)
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#define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64)
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#define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68)
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#define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C)
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#define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70)
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#define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74)
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#define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78)
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#define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C)
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#define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80)
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#define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84)
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#define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88)
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#define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C)
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#define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90)
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#define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94)
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#define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98)
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#define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C)
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#define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0)
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#define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4)
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#define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8)
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#define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC)
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#define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0)
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#define DVFSRC_INT (DVFSRC_BASE + 0xC4)
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#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
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#define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC)
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#define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0)
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#define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4)
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#define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8)
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#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
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#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
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#define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0)
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#define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4)
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#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
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#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
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#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
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#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
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#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
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#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
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#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
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#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
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#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
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#define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200)
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#define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204)
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#define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208)
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#define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C)
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#define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210)
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#define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214)
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#define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218)
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#define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C)
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#define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220)
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#define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224)
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#define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228)
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#define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C)
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#define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230)
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#define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234)
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#define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238)
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#define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C)
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#define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240)
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#define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244)
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#define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248)
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#define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C)
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#define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250)
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#define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254)
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#define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258)
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#define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C)
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#define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260)
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#define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264)
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#define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268)
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#define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C)
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#define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270)
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#define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274)
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#define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278)
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#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
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#define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284)
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#define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290)
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#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
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#define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304)
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#define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308)
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#define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C)
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#define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310)
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#define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314)
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#define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318)
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#define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500)
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#define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504)
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#define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508)
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#define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C)
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#define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510)
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#define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514)
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#define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518)
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#define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C)
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#define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520)
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#define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524)
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#define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528)
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#define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C)
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#define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530)
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#define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534)
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#define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538)
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#define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C)
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#define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540)
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#define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544)
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#define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548)
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#define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600)
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#define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604)
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#define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608)
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#define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C)
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#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
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#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
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#define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630)
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#define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700)
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#define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704)
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#define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708)
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#define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C)
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#define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710)
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#define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800)
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#define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804)
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#define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808)
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#define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C)
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#define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810)
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#define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814)
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#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
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#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
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#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
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#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
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#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
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#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
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#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
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#define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C)
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#define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20)
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#define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24)
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#define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28)
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#define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C)
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#define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30)
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#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
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#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
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#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
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#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
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#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
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#define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48)
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#define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C)
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#define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50)
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#define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54)
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#define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58)
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#define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C)
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#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
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#define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64)
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#define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68)
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#define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C)
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#define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70)
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#define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74)
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#define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78)
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#define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C)
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#define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80)
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#define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84)
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#define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88)
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#define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C)
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#define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90)
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#define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94)
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#define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98)
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#define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C)
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#define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0)
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#define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4)
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#define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8)
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#define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC)
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#define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0)
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#define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4)
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#define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8)
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#define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC)
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#define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0)
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#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
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#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
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#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
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#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
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#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
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#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
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#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
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#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
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#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
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#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
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#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
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#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
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#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
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#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
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#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
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#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
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#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
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#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
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#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
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#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
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#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
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#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
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#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
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#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
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#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
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#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
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#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
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#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
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#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
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#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
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#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
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#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
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#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
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#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
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#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
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#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
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#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
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#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
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#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
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#define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20)
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#define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24)
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#define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28)
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#define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C)
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#define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30)
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#define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34)
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#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
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#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
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#define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40)
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#define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44)
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#define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48)
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#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
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#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
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#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
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#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
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#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
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#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
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#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
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#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
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#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
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#define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70)
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#define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74)
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#define VCORE_VB_EFUSE (0x11C105E8)
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#endif /* MT_SPM_VCOREFS_H */
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