97 lines
3.0 KiB
C
97 lines
3.0 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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const unsigned char tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* No of CPU cores */
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PLATFORM_CORE_COUNT,
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};
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/* sets of MMIO ranges setup */
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#define MMIO_RANGE_0_ADDR 0x50000000
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#define MMIO_RANGE_1_ADDR 0x60000000
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#define MMIO_RANGE_2_ADDR 0x70000000
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#define MMIO_RANGE_SIZE 0x200000
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/*
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Set up the pagetables as per the platform memory map & initialize the MMU
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******************************************************************************/
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const mmap_region_t *plat_get_mmio_map(void)
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{
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/* MMIO space */
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return tegra_mmap;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return 12000000;
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}
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/*******************************************************************************
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* Maximum supported UART controllers
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******************************************************************************/
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#define TEGRA132_MAX_UART_PORTS 5
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/*******************************************************************************
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* This variable holds the UART port base addresses
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******************************************************************************/
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static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
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0, /* undefined - treated as an error case */
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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TEGRA_UARTC_BASE,
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TEGRA_UARTD_BASE,
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TEGRA_UARTE_BASE,
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};
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/*******************************************************************************
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* Retrieve the UART controller base to be used as the console
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******************************************************************************/
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uint32_t plat_get_console_from_id(int id)
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{
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if (id > TEGRA132_MAX_UART_PORTS)
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return 0;
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return tegra132_uart_addresses[id];
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}
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/*******************************************************************************
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* Initialize the GIC and SGIs
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******************************************************************************/
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void plat_gic_setup(void)
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{
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tegra_gic_setup(NULL, 0);
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}
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