341 lines
6.3 KiB
C
341 lines
6.3 KiB
C
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <string.h>
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#include <common/debug.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat_private.h>
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#include <plat/common/platform.h>
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#include "pm_api_sys.h"
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_arm_mmap[] = {
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{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{ CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
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{0}
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};
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static unsigned int zynqmp_get_silicon_ver(void)
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{
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static unsigned int ver;
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if (!ver) {
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +
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ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_SILICON_VER_MASK;
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ver >>= ZYNQMP_SILICON_VER_SHIFT;
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}
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return ver;
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}
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unsigned int zynqmp_get_uart_clk(void)
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{
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unsigned int ver = zynqmp_get_silicon_ver();
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if (ver == ZYNQMP_CSU_VERSION_QEMU)
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return 133000000;
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else
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return 100000000;
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}
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#if LOG_LEVEL >= LOG_LEVEL_NOTICE
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static const struct {
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unsigned int id;
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unsigned int ver;
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char *name;
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bool evexists;
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} zynqmp_devices[] = {
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{
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.id = 0x10,
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.name = "3EG",
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},
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{
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.id = 0x10,
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.ver = 0x2c,
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.name = "3CG",
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},
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{
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.id = 0x11,
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.name = "2EG",
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},
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{
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.id = 0x11,
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.ver = 0x2c,
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.name = "2CG",
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},
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{
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.id = 0x20,
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.name = "5EV",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x100,
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.name = "5EG",
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.evexists = true,
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},
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{
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.id = 0x20,
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.ver = 0x12c,
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.name = "5CG",
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},
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{
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.id = 0x21,
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.name = "4EV",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x100,
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.name = "4EG",
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.evexists = true,
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},
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{
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.id = 0x21,
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.ver = 0x12c,
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.name = "4CG",
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},
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{
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.id = 0x30,
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.name = "7EV",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x100,
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.name = "7EG",
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.evexists = true,
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},
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{
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.id = 0x30,
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.ver = 0x12c,
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.name = "7CG",
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},
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{
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.id = 0x38,
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.name = "9EG",
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},
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{
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.id = 0x38,
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.ver = 0x2c,
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.name = "9CG",
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},
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{
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.id = 0x39,
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.name = "6EG",
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},
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{
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.id = 0x39,
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.ver = 0x2c,
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.name = "6CG",
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},
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{
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.id = 0x40,
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.name = "11EG",
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},
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{ /* For testing purpose only */
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.id = 0x50,
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.ver = 0x2c,
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.name = "15CG",
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},
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{
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.id = 0x50,
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.name = "15EG",
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},
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{
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.id = 0x58,
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.name = "19EG",
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},
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{
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.id = 0x59,
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.name = "17EG",
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},
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{
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.id = 0x60,
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.name = "28DR",
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},
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{
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.id = 0x61,
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.name = "21DR",
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},
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{
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.id = 0x62,
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.name = "29DR",
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},
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{
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.id = 0x63,
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.name = "23DR",
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},
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{
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.id = 0x64,
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.name = "27DR",
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},
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{
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.id = 0x65,
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.name = "25DR",
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},
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};
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#define ZYNQMP_PL_STATUS_BIT 9
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#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
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#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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uint32_t id, ver, chipid[2];
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size_t i, j, len;
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const char *name = "EG/EV";
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#ifdef IMAGE_BL32
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/*
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* For BL32, get the chip id info directly by reading corresponding
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* registers instead of making pm call. This has limitation
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* that these registers should be configured to have access
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* from APU which is default case.
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*/
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chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
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#else
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if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
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return "UNKN";
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#endif
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id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
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ZYNQMP_CSU_IDCODE_SVD_MASK);
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id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
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ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == id &&
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zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))
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break;
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}
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if (i >= ARRAY_SIZE(zynqmp_devices))
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return "UNKN";
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if (!zynqmp_devices[i].evexists)
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return zynqmp_devices[i].name;
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if (ver & ZYNQMP_PL_STATUS_MASK)
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return zynqmp_devices[i].name;
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len = strlen(zynqmp_devices[i].name) - 2;
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for (j = 0; j < strlen(name); j++) {
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zynqmp_devices[i].name[len] = name[j];
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len++;
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}
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zynqmp_devices[i].name[len] = '\0';
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return zynqmp_devices[i].name;
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}
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static unsigned int zynqmp_get_rtl_ver(void)
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{
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uint32_t ver;
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ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_RTL_VER_MASK;
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ver >>= ZYNQMP_RTL_VER_SHIFT;
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return ver;
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}
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static char *zynqmp_print_silicon_idcode(void)
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{
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uint32_t id, maskid, tmp;
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id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
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tmp = id;
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tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK |
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ZYNQMP_CSU_IDCODE_FAMILY_MASK;
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maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT |
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ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT;
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if (tmp != maskid) {
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ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid);
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return "UNKN";
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}
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VERBOSE("Xilinx IDCODE 0x%x\n", id);
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return zynqmp_get_silicon_idcode_name();
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}
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static unsigned int zynqmp_get_ps_ver(void)
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{
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uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);
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ver &= ZYNQMP_PS_VER_MASK;
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ver >>= ZYNQMP_PS_VER_SHIFT;
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return ver + 1;
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}
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static void zynqmp_print_platform_name(void)
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{
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unsigned int ver = zynqmp_get_silicon_ver();
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unsigned int rtl = zynqmp_get_rtl_ver();
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char *label = "Unknown";
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switch (ver) {
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case ZYNQMP_CSU_VERSION_QEMU:
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label = "QEMU";
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break;
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case ZYNQMP_CSU_VERSION_SILICON:
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label = "silicon";
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
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zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
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(rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
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}
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#else
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static inline void zynqmp_print_platform_name(void) { }
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#endif
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unsigned int zynqmp_get_bootmode(void)
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{
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uint32_t r;
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unsigned int ret;
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ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r);
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if (ret != PM_RET_SUCCESS)
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r = mmio_read_32(CRL_APB_BOOT_MODE_USER);
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return r & CRL_APB_BOOT_MODE_MASK;
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}
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void zynqmp_config_setup(void)
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{
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zynqmp_print_platform_name();
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generic_delay_timer_init();
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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unsigned int ver = zynqmp_get_silicon_ver();
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if (ver == ZYNQMP_CSU_VERSION_QEMU)
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return 50000000;
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else
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return mmio_read_32(IOU_SCNTRS_BASEFREQ);
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}
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