Louis Mayencourt 5c6aa01aff Add workaround for errata 1073348 for Cortex-A76 ... Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-02-26 16:21:06 +00:00
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aarch32	cpus: Add casts to all definitions in CPU headers	2019-02-11 13:34:57 +00:00
aarch64	Add workaround for errata 1073348 for Cortex-A76	2019-02-26 16:21:06 +00:00
errata_report.h	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00