johpow01 e16045de50 fix(errata): workaround for Cortex X2 erratum 2058056 ... Cortex X2 erratum 2058056 is a Cat B erratum present in the X2 core. It applies to revisions r0p0, r1p0, and r2p0 and is still open. There are 2 ways this workaround can be accomplished, the first of which involves executing a few additional instructions around MSR writes to CPUECTLR when disabling the prefetcher. (see SDEN for details) However, this patch implements the 2nd possible workaround which sets the prefetcher into its most conservative mode, since this workaround is generic. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775100 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3		2021-12-21 11:52:26 -06:00
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aarch32	lib: cpus: aarch32: sanity check pointers before use	2021-02-23 15:16:51 +01:00
aarch64	fix(errata): workaround for Cortex X2 erratum 2058056	2021-12-21 11:52:26 -06:00
cpu-ops.mk	fix(errata): workaround for Cortex X2 erratum 2058056	2021-12-21 11:52:26 -06:00
errata_report.c	fix(errata_report): correct typo	2021-10-06 17:35:39 +02:00