551 lines
19 KiB
C
551 lines
19 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <assert.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_pmic_wrap.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_resource_req.h>
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#include <platform_def.h>
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#include <plat_pm.h>
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/**************************************
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* Define and Declare
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**************************************/
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#define ROOT_CORE_ADDR_OFFSET 0x20000000
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#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
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#define SPM_INIT_DONE_US 20
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#define SPM_WAKEUP_REASON_MISSING 0xdeaddead
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static unsigned int mt_spm_bblpm_cnt;
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const char *wakeup_src_str[32] = {
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[0] = "PCM_TIMER",
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[1] = "RESERVED_DEBUG_B",
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[2] = "KEYPAD",
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[3] = "APWDT",
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[4] = "APXGPT",
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[5] = "MSDC",
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[6] = "EINT",
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[7] = "IRRX",
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[8] = "ETHERNET_QOS",
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[9] = "RESERVE0",
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[10] = "SSPM",
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[11] = "SCP",
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[12] = "ADSP",
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[13] = "SPM_WDT",
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[14] = "USB_U2",
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[15] = "USB_TOP",
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[16] = "SYS_TIMER",
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[17] = "EINT_SECURE",
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[18] = "HDMI",
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[19] = "RESERVE1",
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[20] = "AFE",
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[21] = "THERMAL",
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[22] = "SYS_CIRQ",
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[23] = "NNA2INFRA",
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[24] = "CSYSPWREQ",
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[25] = "RESERVE2",
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[26] = "PCIE",
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[27] = "SEJ",
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[28] = "SPM_CPU_WAKEUPEVENT",
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[29] = "APUSYS",
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[30] = "RESERVE3",
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[31] = "RESERVE4",
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};
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/**************************************
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* Function and API
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**************************************/
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wake_reason_t __spm_output_wake_reason(int state_id,
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const struct wake_status *wakesta)
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{
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uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
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char *spm_26m_sta = NULL;
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wake_reason_t wr = WR_UNKNOWN;
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if (wakesta == NULL) {
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return WR_UNKNOWN;
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}
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spm_26m_sta = ((wakesta->debug_flag & SPM_DBG_DEBUG_IDX_26M_SLEEP) == 0U) ? "on" : "off";
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if (wakesta->abort != 0U) {
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ERROR("spmfw flow is aborted: 0x%x, timer_out = %u, 26M(%s)\n",
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wakesta->abort, wakesta->timer_out, spm_26m_sta);
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} else if (wakesta->r12 == SPM_WAKEUP_REASON_MISSING) {
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WARN("cannot find wake up reason, timer_out = %u, 26M(%s)\n",
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wakesta->timer_out, spm_26m_sta);
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} else {
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for (i = 0U; i < 32U; i++) {
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if ((wakesta->r12 & (1U << i)) != 0U) {
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INFO("wake up by %s, timer_out = %u, 26M(%s)\n",
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wakeup_src_str[i], wakesta->timer_out, spm_26m_sta);
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wr = WR_WAKE_SRC;
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break;
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}
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}
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}
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INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
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wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
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wakesta->debug_flag1);
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INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
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wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
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wakesta->md32pcm_event_sta, wakesta->idle_sta,
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wakesta->cg_check_sta);
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INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
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wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
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wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
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INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
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wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
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INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
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wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
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INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
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wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
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wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
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INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
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wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
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mmio_read_32(SYS_TIMER_VALUE_H));
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if (wakesta->timer_out != 0U) {
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bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
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spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
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INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
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}
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return wr;
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}
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void __spm_set_cpu_status(unsigned int cpu)
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{
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uint32_t root_core_addr;
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if (cpu < 8U) {
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mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
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root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
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root_core_addr += ROOT_CORE_ADDR_OFFSET;
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mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
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/* Notify MCUPM that preferred cpu wakeup */
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mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
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} else {
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ERROR("%s: error cpu number %d\n", __func__, cpu);
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}
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}
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void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
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unsigned int resource_usage)
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{
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uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
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1 : pwrctrl->reg_spm_apsrc_req;
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uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
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1 : pwrctrl->reg_spm_ddr_en_req;
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uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
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1 : pwrctrl->reg_spm_vrf18_req;
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uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
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1 : pwrctrl->reg_spm_infra_req;
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uint8_t f26m_req = ((resource_usage &
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(MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
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1 : pwrctrl->reg_spm_f26m_req;
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mmio_write_32(SPM_SRC_REQ,
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((apsrc_req & 0x1) << 0) |
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((f26m_req & 0x1) << 1) |
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((infra_req & 0x1) << 3) |
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((vrf18_req & 0x1) << 4) |
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((ddr_en_req & 0x1) << 7) |
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((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
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((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
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((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
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((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
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((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
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}
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void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
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{
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/* Auto-gen Start */
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/* SPM_AP_STANDBY_CON */
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mmio_write_32(SPM_AP_STANDBY_CON,
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((pwrctrl->reg_wfi_op & 0x1) << 0) |
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((pwrctrl->reg_wfi_type & 0x1) << 1) |
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((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
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((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
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((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
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((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
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((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
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((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
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/* SPM_SRC_REQ */
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mmio_write_32(SPM_SRC_REQ,
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((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
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((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
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((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
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((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
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((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
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((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
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((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
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((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
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((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
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((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
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/* SPM_SRC_MASK */
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mmio_write_32(SPM_SRC_MASK,
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((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
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((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
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((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
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((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
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((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
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((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
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((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
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((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
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((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
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((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
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((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
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((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
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((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
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((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
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((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
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((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
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((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
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((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
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((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
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((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
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((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
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((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
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((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
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((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
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((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
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((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
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((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
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((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
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((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
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((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
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/* SPM_SRC2_MASK */
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mmio_write_32(SPM_SRC2_MASK,
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((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
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((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
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((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
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((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
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((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
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((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
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((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
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((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
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((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
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((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
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((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
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((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
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((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
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((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
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((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
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((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
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((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
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((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
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((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
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((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
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((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
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((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
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((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
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((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
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((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
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((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
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((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
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((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
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((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
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((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
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/* SPM_SRC3_MASK */
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mmio_write_32(SPM_SRC3_MASK,
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((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
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((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
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((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
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((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
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((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
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((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
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((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
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((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
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((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
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((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
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((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
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((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
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((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
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((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
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((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
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((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
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((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
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((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
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((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
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((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
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((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
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((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
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((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
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((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
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((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
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((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
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((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
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((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
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/* Mask MCUSYS request since SOC HW would check it */
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mmio_write_32(SPM_SRC4_MASK, 0x1fc0000);
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/* SPM_WAKEUP_EVENT_MASK */
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mmio_write_32(SPM_WAKEUP_EVENT_MASK,
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((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
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((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
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/* Auto-gen End */
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}
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void __spm_disable_pcm_timer(void)
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{
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mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
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}
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void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
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{
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uint32_t val, mask;
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/* toggle event counter clear */
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mmio_setbits_32(PCM_CON1,
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SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
|
|
|
|
/* toggle for reset SYS TIMER start point */
|
|
mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
|
|
|
|
if (pwrctrl->timer_val_cust == 0U) {
|
|
val = pwrctrl->timer_val;
|
|
} else {
|
|
val = pwrctrl->timer_val_cust;
|
|
}
|
|
|
|
mmio_write_32(PCM_TIMER_VAL, val);
|
|
mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
|
|
|
|
/* unmask AP wakeup source */
|
|
if (pwrctrl->wake_src_cust == 0U) {
|
|
mask = pwrctrl->wake_src;
|
|
} else {
|
|
mask = pwrctrl->wake_src_cust;
|
|
}
|
|
|
|
mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
|
|
|
|
/* unmask SPM ISR (keep TWAM setting) */
|
|
mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
|
|
|
|
/* toggle event counter clear */
|
|
mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
|
|
SPM_REGWR_CFG_KEY);
|
|
/* toggle for reset SYS TIMER start point */
|
|
mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
|
|
}
|
|
|
|
void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
|
|
{
|
|
/* set PCM flags and data */
|
|
if (pwrctrl->pcm_flags_cust_clr != 0U) {
|
|
pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
|
|
}
|
|
|
|
if (pwrctrl->pcm_flags_cust_set != 0U) {
|
|
pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
|
|
}
|
|
|
|
if (pwrctrl->pcm_flags1_cust_clr != 0U) {
|
|
pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
|
|
}
|
|
|
|
if (pwrctrl->pcm_flags1_cust_set != 0U) {
|
|
pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
|
|
}
|
|
|
|
mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
|
|
mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
|
|
mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
|
|
mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
|
|
}
|
|
|
|
void __spm_get_wakeup_status(struct wake_status *wakesta,
|
|
unsigned int ext_status)
|
|
{
|
|
wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
|
|
wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
|
|
wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
|
|
wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
|
|
wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
|
|
wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
|
|
wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
|
|
wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
|
|
wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
|
|
wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
|
|
|
|
if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
|
|
wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
|
|
SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
|
|
mmio_write_32(PCM_WDT_LATCH_SPARE_0,
|
|
wakesta->tr.comm.debug_flag);
|
|
}
|
|
|
|
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
|
|
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
|
|
|
|
/* record below spm info for debug */
|
|
wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
|
|
wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
|
|
wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
|
|
wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
|
|
wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
|
|
wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
|
|
wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
|
|
|
|
/* backup of SPM_WAKEUP_MISC */
|
|
wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
|
|
|
|
/* get sleep time, backup of PCM_TIMER_OUT */
|
|
wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
|
|
|
|
/* get other SYS and co-clock status */
|
|
wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
|
|
wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
|
|
wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
|
|
wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
|
|
wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
|
|
wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
|
|
wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
|
|
|
|
/* get HW CG check status */
|
|
wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
|
|
|
|
/* get debug flag for PCM execution check */
|
|
wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
|
|
wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
|
|
|
|
/* get backup SW flag status */
|
|
wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
|
|
wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
|
|
|
|
wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
|
|
wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
|
|
wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
|
|
wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
|
|
wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
|
|
|
|
/* get ISR status */
|
|
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
|
|
|
|
/* get SW flag status */
|
|
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
|
|
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
|
|
|
|
/* get CLK SETTLE */
|
|
wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
|
|
|
|
/* check abort */
|
|
wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
|
|
(wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
|
|
}
|
|
|
|
void __spm_clean_after_wakeup(void)
|
|
{
|
|
mmio_write_32(SPM_BK_WAKE_EVENT,
|
|
mmio_read_32(SPM_WAKEUP_STA) |
|
|
mmio_read_32(SPM_BK_WAKE_EVENT));
|
|
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
|
|
|
|
/*
|
|
* clean wakeup event raw status (for edge trigger event)
|
|
* bit[28] for cpu wake up event
|
|
*/
|
|
mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
|
|
|
|
/* clean ISR status (except TWAM) */
|
|
mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
|
|
mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
|
|
mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
|
|
}
|
|
|
|
void __spm_set_pcm_wdt(int en)
|
|
{
|
|
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
|
|
SPM_REGWR_CFG_KEY);
|
|
|
|
if (en == 1) {
|
|
mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
|
|
SPM_REGWR_CFG_KEY);
|
|
|
|
if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
|
|
mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
|
|
}
|
|
|
|
mmio_write_32(PCM_WDT_VAL,
|
|
mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
|
|
mmio_setbits_32(PCM_CON1,
|
|
SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
|
|
}
|
|
}
|
|
|
|
void __spm_send_cpu_wakeup_event(void)
|
|
{
|
|
/* SPM will clear SPM_CPU_WAKEUP_EVENT */
|
|
mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
|
|
}
|
|
|
|
void __spm_ext_int_wakeup_req_clr(void)
|
|
{
|
|
mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
|
|
|
|
/* Clear spm2mcupm wakeup interrupt status */
|
|
mmio_write_32(SPM2CPUEB_CON, 0);
|
|
}
|
|
|
|
void __spm_xo_soc_bblpm(int en)
|
|
{
|
|
if (en == 1) {
|
|
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
|
|
RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
|
|
assert(mt_spm_bblpm_cnt == 0);
|
|
mt_spm_bblpm_cnt += 1;
|
|
} else {
|
|
mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
|
|
RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
|
|
mt_spm_bblpm_cnt -= 1;
|
|
}
|
|
}
|
|
|
|
void __spm_hw_s1_state_monitor(int en, unsigned int *status)
|
|
{
|
|
unsigned int reg;
|
|
|
|
reg = mmio_read_32(SPM_ACK_CHK_CON_3);
|
|
|
|
if (en == 1) {
|
|
reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
|
|
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
|
|
reg |= SPM_ACK_CHK_3_CON_EN;
|
|
mmio_write_32(SPM_ACK_CHK_CON_3, reg);
|
|
} else {
|
|
if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
|
|
(status != NULL)) {
|
|
*status |= SPM_INTERNAL_STATUS_HW_S1;
|
|
}
|
|
|
|
mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
|
|
SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
|
|
SPM_ACK_CHK_3_CON_CLR_ALL);
|
|
}
|
|
}
|