282 lines
12 KiB
C
282 lines
12 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_DEF_H
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#define TEGRA_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Power down state IDs
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******************************************************************************/
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#define PSTATE_ID_CORE_POWERDN U(7)
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#define PSTATE_ID_CLUSTER_IDLE U(16)
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#define PSTATE_ID_SOC_POWERDN U(27)
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/*******************************************************************************
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* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call as the `state-id` field in the 'power state' parameter.
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******************************************************************************/
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#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
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/*******************************************************************************
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* Chip specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
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/*******************************************************************************
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* SC7 entry firmware's header size
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******************************************************************************/
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#define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
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/*******************************************************************************
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* iRAM memory constants
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******************************************************************************/
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#define TEGRA_IRAM_BASE U(0x40000000)
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#define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */
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#define TEGRA_IRAM_SIZE U(40000) /* 256KB */
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/*******************************************************************************
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* GIC memory map
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******************************************************************************/
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#define TEGRA_GICD_BASE U(0x50041000)
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#define TEGRA_GICC_BASE U(0x50042000)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA210_WDT_CPU_LEGACY_FIQ U(28)
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/*******************************************************************************
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* Tegra Memory Select Switch Controller constants
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******************************************************************************/
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#define TEGRA_MSELECT_BASE U(0x50060000)
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#define MSELECT_CONFIG U(0x0)
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#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
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#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
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#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
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#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
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#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
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#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
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UNSUPPORTED_TX_ERR_MASTER1_BIT)
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#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
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ENABLE_WRAP_INCR_MASTER1_BIT | \
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ENABLE_WRAP_INCR_MASTER0_BIT)
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/*******************************************************************************
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* Tegra Resource Semaphore constants
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******************************************************************************/
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#define TEGRA_RES_SEMA_BASE 0x60001000UL
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#define STA_OFFSET 0UL
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#define SET_OFFSET 4UL
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#define CLR_OFFSET 8UL
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/*******************************************************************************
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* Tegra Primary Interrupt Controller constants
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******************************************************************************/
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#define TEGRA_PRI_ICTLR_BASE 0x60004000UL
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#define CPU_IEP_FIR_SET 0x18UL
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE U(0x60005010)
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#define TEGRA_TMRUS_SIZE U(0x1000)
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x60006000)
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#define TEGRA_BOND_OUT_H U(0x74)
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#define APB_DMA_LOCK_BIT (U(1) << 2)
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#define AHB_DMA_LOCK_BIT (U(1) << 1)
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#define TEGRA_BOND_OUT_U U(0x78)
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#define IRAM_D_LOCK_BIT (U(1) << 23)
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#define IRAM_C_LOCK_BIT (U(1) << 22)
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#define IRAM_B_LOCK_BIT (U(1) << 21)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
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#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
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#define GPU_RESET_BIT (U(1) << 24)
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#define GPU_SET_BIT (U(1) << 24)
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#define TEGRA_RST_DEV_SET_Y U(0x2a8)
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#define NVENC_RESET_BIT (U(1) << 27)
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#define TSECB_RESET_BIT (U(1) << 14)
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#define APE_RESET_BIT (U(1) << 6)
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#define NVJPG_RESET_BIT (U(1) << 3)
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#define NVDEC_RESET_BIT (U(1) << 2)
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#define TEGRA_RST_DEV_SET_L U(0x300)
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#define HOST1X_RESET_BIT (U(1) << 28)
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#define ISP_RESET_BIT (U(1) << 23)
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#define USBD_RESET_BIT (U(1) << 22)
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#define VI_RESET_BIT (U(1) << 20)
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#define SDMMC4_RESET_BIT (U(1) << 15)
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#define SDMMC1_RESET_BIT (U(1) << 14)
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#define SDMMC2_RESET_BIT (U(1) << 9)
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#define TEGRA_RST_DEV_SET_H U(0x308)
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#define USB2_RESET_BIT (U(1) << 26)
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#define APBDMA_RESET_BIT (U(1) << 2)
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#define AHBDMA_RESET_BIT (U(1) << 1)
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#define TEGRA_RST_DEV_SET_U U(0x310)
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#define XUSB_DEV_RESET_BIT (U(1) << 31)
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#define XUSB_HOST_RESET_BIT (U(1) << 25)
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#define TSEC_RESET_BIT (U(1) << 19)
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#define PCIE_RESET_BIT (U(1) << 6)
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#define SDMMC3_RESET_BIT (U(1) << 5)
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#define TEGRA_RST_DEVICES_V U(0x358)
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#define TEGRA_RST_DEVICES_W U(0x35C)
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#define ENTROPY_CLK_ENB_BIT (U(1) << 21)
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#define TEGRA_CLK_OUT_ENB_V U(0x360)
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#define SE_CLK_ENB_BIT (U(1) << 31)
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#define TEGRA_CLK_OUT_ENB_W U(0x364)
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#define ENTROPY_RESET_BIT (U(1) << 21)
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#define TEGRA_CLK_RST_CTL_CLK_SRC_SE U(0x42C)
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#define SE_CLK_SRC_MASK (U(7) << 29)
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#define SE_CLK_SRC_CLK_M (U(6) << 29)
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#define TEGRA_RST_DEV_SET_V U(0x430)
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#define SE_RESET_BIT (U(1) << 31)
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#define HDA_RESET_BIT (U(1) << 29)
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#define SATA_RESET_BIT (U(1) << 28)
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#define TEGRA_RST_DEV_CLR_V U(0x434)
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#define TEGRA_CLK_ENB_V U(0x440)
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/*******************************************************************************
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* Tegra Flow Controller constants
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******************************************************************************/
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#define TEGRA_FLOWCTRL_BASE U(0x60007000)
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/*******************************************************************************
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* Tegra AHB arbitration controller
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******************************************************************************/
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#define TEGRA_AHB_ARB_BASE 0x6000C000UL
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/*******************************************************************************
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* Tegra Secure Boot Controller constants
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******************************************************************************/
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#define TEGRA_SB_BASE U(0x6000C200)
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/*******************************************************************************
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* Tegra Exception Vectors constants
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******************************************************************************/
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#define TEGRA_EVP_BASE U(0x6000F000)
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/*******************************************************************************
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* Tegra Miscellaneous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x70000000)
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#define HARDWARE_REVISION_OFFSET U(0x804)
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#define APB_SLAVE_SECURITY_ENABLE U(0xC00)
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#define PMC_SECURITY_EN_BIT (U(1) << 13)
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#define PINMUX_AUX_DVFS_PWM U(0x3184)
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#define PINMUX_PWM_TRISTATE (U(1) << 4)
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/*******************************************************************************
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* Tegra UART controller base addresses
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******************************************************************************/
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#define TEGRA_UARTA_BASE U(0x70006000)
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#define TEGRA_UARTB_BASE U(0x70006040)
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#define TEGRA_UARTC_BASE U(0x70006200)
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#define TEGRA_UARTD_BASE U(0x70006300)
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#define TEGRA_UARTE_BASE U(0x70006400)
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/*******************************************************************************
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* Tegra Fuse Controller related constants
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******************************************************************************/
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#define TEGRA_FUSE_BASE 0x7000F800UL
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#define FUSE_BOOT_SECURITY_INFO 0x268UL
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#define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7)
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#define FUSE_JTAG_SECUREID_VALID (0x104UL)
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#define ECID_VALID (0x1UL)
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x7000E400)
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#define TEGRA_PMC_SIZE U(0xC00) /* 3k */
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/*******************************************************************************
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* Tegra Atomics constants
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******************************************************************************/
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#define TEGRA_ATOMICS_BASE 0x70016000UL
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#define TRIGGER0_REG_OFFSET 0UL
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#define TRIGGER_WIDTH_SHIFT 4UL
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#define TRIGGER_ID_SHIFT 16UL
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#define RESULT0_REG_OFFSET 0xC00UL
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_BASE U(0x70019000)
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/* Memory Controller Interrupt Status */
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#define MC_INTSTATUS 0x00U
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 U(0x70)
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#define MC_SECURITY_CFG1_0 U(0x74)
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#define MC_SECURITY_CFG3_0 U(0x9BC)
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
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#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
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#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
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/* SMMU configuration registers*/
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#define MC_SMMU_PPCS_ASID_0 0x270U
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#define PPCS_SMMU_ENABLE (0x1U << 31)
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/*******************************************************************************
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* Tegra CLDVFS constants
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******************************************************************************/
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#define TEGRA_CL_DVFS_BASE U(0x70110000)
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#define DVFS_DFLL_CTRL U(0x00)
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#define ENABLE_OPEN_LOOP U(1)
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#define ENABLE_CLOSED_LOOP U(2)
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#define DVFS_DFLL_OUTPUT_CFG U(0x20)
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#define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30)
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#define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6)
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/*******************************************************************************
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* Tegra SE constants
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******************************************************************************/
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#define TEGRA_SE1_BASE U(0x70012000)
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#define TEGRA_SE2_BASE U(0x70412000)
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#define TEGRA_PKA1_BASE U(0x70420000)
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#define TEGRA_SE2_RANGE_SIZE U(0x2000)
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#define SE_TZRAM_SECURITY U(0x4)
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE U(0x7C010000)
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#define TEGRA_TZRAM_SIZE U(0x10000)
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/*******************************************************************************
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* Tegra TZRAM carveout constants
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******************************************************************************/
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#define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000)
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#define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000)
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/*******************************************************************************
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* Tegra DRAM memory base address
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******************************************************************************/
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#define TEGRA_DRAM_BASE ULL(0x80000000)
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#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
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#endif /* TEGRA_DEF_H */
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