346 lines
12 KiB
C
346 lines
12 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/ep_info.h>
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#include <common/interrupt_props.h>
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#include <context.h>
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#include <cortex_a57.h>
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#include <denver.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/console.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <mce.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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/*******************************************************************************
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* Tegra186 CPU numbers in cluster #0
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*******************************************************************************
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*/
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#define TEGRA186_CLUSTER0_CORE2 2U
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#define TEGRA186_CLUSTER0_CORE3 3U
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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static const uint8_t tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* No of CPU cores - cluster0 */
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PLATFORM_MAX_CPUS_PER_CLUSTER,
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/* No of CPU cores - cluster1 */
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PLATFORM_MAX_CPUS_PER_CLUSTER
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};
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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******************************************************************************/
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const uint8_t *plat_get_power_domain_tree_desc(void)
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{
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return tegra_power_domain_tree_desc;
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}
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/*
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
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MT_DEVICE | MT_RO | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Set up the pagetables as per the platform memory map & initialize the MMU
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******************************************************************************/
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const mmap_region_t *plat_get_mmio_map(void)
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{
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/* MMIO space */
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return tegra_mmap;
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}
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/*******************************************************************************
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* Handler to get the System Counter Frequency
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******************************************************************************/
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uint32_t plat_get_syscnt_freq2(void)
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{
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return 31250000;
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}
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/*******************************************************************************
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* Maximum supported UART controllers
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******************************************************************************/
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#define TEGRA186_MAX_UART_PORTS 7
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/*******************************************************************************
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* This variable holds the UART port base addresses
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******************************************************************************/
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static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
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0, /* undefined - treated as an error case */
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TEGRA_UARTA_BASE,
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TEGRA_UARTB_BASE,
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TEGRA_UARTC_BASE,
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TEGRA_UARTD_BASE,
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TEGRA_UARTE_BASE,
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TEGRA_UARTF_BASE,
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TEGRA_UARTG_BASE,
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};
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/*******************************************************************************
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* Enable console corresponding to the console ID
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******************************************************************************/
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void plat_enable_console(int32_t id)
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{
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static console_t uart_console;
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uint32_t console_clock;
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if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
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/*
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* Reference clock used by the FPGAs is a lot slower.
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*/
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if (tegra_platform_is_fpga()) {
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console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
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} else {
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console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
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}
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(void)console_16550_register(tegra186_uart_addresses[id],
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console_clock,
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TEGRA_CONSOLE_BAUDRATE,
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&uart_console);
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console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
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}
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}
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/*******************************************************************************
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* Handler for early platform setup
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******************************************************************************/
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void plat_early_platform_setup(void)
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{
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uint64_t impl, val;
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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/* sanity check MCE firmware compatibility */
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mce_verify_firmware_version();
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impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
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/*
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* Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
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* A02p and beyond).
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*/
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if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
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(impl != (uint64_t)DENVER_IMPL)) {
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val = read_l2ctlr_el1();
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val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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}
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}
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/*******************************************************************************
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* Handler for late platform setup
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******************************************************************************/
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void plat_late_platform_setup(void)
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{
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; /* do nothing */
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}
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/* Secure IRQs for Tegra186 */
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static const interrupt_prop_t tegra186_interrupt_props[] = {
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INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
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};
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/*******************************************************************************
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* Initialize the GIC and SGIs
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******************************************************************************/
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void plat_gic_setup(void)
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{
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tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
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tegra_gic_init();
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/*
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* Initialize the FIQ handler only if the platform supports any
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* FIQ interrupt sources.
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*/
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tegra_fiq_handler_setup();
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}
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/*******************************************************************************
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* Return pointer to the BL31 params from previous bootloader
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******************************************************************************/
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
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return (struct tegra_bl31_params *)(uintptr_t)val;
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}
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/*******************************************************************************
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* Return pointer to the BL31 platform params from previous bootloader
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******************************************************************************/
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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uint32_t val;
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val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
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return (plat_params_from_bl2_t *)(uintptr_t)val;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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u_register_t cluster_id, cpu_id, pos;
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int32_t ret;
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cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
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/*
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* Validate cluster_id by checking whether it represents
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* one of the two clusters present on the platform.
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
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(cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
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ret = PSCI_E_NOT_PRESENT;
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} else {
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/* calculate the core position */
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pos = cpu_id + (cluster_id << 2U);
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/* check for non-existent CPUs */
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if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
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ret = PSCI_E_NOT_PRESENT;
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} else {
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ret = (int32_t)pos;
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}
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}
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return ret;
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}
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/*******************************************************************************
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* Handler to relocate BL32 image to TZDRAM
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******************************************************************************/
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void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
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{
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const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
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const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
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/* Relocate BL32 if it resides outside of the TZDRAM */
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tzdram_start = plat_bl31_params->tzdram_base;
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tzdram_end = plat_bl31_params->tzdram_base +
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plat_bl31_params->tzdram_size;
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bl32_start = bl32_img_info->image_base;
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bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
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assert(tzdram_end > tzdram_start);
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assert(bl32_end > bl32_start);
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assert(bl32_ep_info->pc > tzdram_start);
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assert(bl32_ep_info->pc < tzdram_end);
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/* relocate BL32 */
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if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
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INFO("Relocate BL32 to TZDRAM\n");
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(void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
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(void *)(uintptr_t)bl32_start,
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bl32_img_info->image_size);
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/* clean up non-secure intermediate buffer */
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zeromem((void *)(uintptr_t)bl32_start,
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bl32_img_info->image_size);
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}
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}
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}
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/*******************************************************************************
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* Handler to indicate support for System Suspend
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******************************************************************************/
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bool plat_supports_system_suspend(void)
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{
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return true;
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}
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