1552df5d25
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> |
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.. | ||
svc | ||
imx8_mu.c | ||
imx8_mu.h | ||
ipc.c | ||
sci_api.mk |