Andrew F. Davis 65f7b81728 ti: k3: common: Use coherent memory for shared data ... HW_ASSISTED_COHERENCY implies something stronger than just hardware coherent interconnect, specifically a DynamIQ capable ARM core. For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early and then let the caches get shut off on powerdown, to prevent data corruption we also need to USE_COHERENT_MEM so that any accesses to shared memory after this point is only to memory that is set as non-cached for all cores. Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949 Signed-off-by: Andrew F. Davis <afd@ti.com>		2019-06-06 11:20:21 +01:00
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drivers	ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID	2019-04-23 11:09:13 -04:00
k3_bl31_setup.c	ti: k3: common: Allow USE_COHERENT_MEM for K3	2019-04-26 11:50:13 -04:00
k3_console.c	ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines	2019-04-19 12:56:24 -04:00
k3_gicv3.c	ti: k3: common: Add support for runtime detection of GICR base address	2019-01-22 13:11:09 -06:00
k3_helpers.S	ti: k3: common: Set L2 latency on A72 cores	2019-05-22 12:07:52 -05:00
k3_psci.c	ti: k3: common: Mark sections for AM65x coherency workaround	2019-04-26 11:52:25 -04:00
k3_topology.c	ti: k3: common: Remove MSMC port definitions	2019-04-30 09:41:06 -04:00
plat_common.mk	ti: k3: common: Use coherent memory for shared data	2019-06-06 11:20:21 +01:00