193 lines
4.7 KiB
C
193 lines
4.7 KiB
C
/*
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* Copyright (c) 2019, Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal PM nodes enums and defines */
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#ifndef PM_NODE_H
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#define PM_NODE_H
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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#define NODE_CLASS_SHIFT 26U
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#define NODE_SUBCLASS_SHIFT 20U
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#define NODE_TYPE_SHIFT 14U
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#define NODE_INDEX_SHIFT 0U
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#define NODE_CLASS_MASK_BITS 0x3F
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#define NODE_SUBCLASS_MASK_BITS 0x3F
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#define NODE_TYPE_MASK_BITS 0x3F
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#define NODE_INDEX_MASK_BITS 0x3FFF
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#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
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#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
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#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
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#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
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#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
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((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
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(((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
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(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
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(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
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#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
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#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
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NODE_SUBCLASS_SHIFT)
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#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
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#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/* Node class types */
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enum pm_node_class {
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XPM_NODECLASS_MIN,
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XPM_NODECLASS_POWER,
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XPM_NODECLASS_CLOCK,
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XPM_NODECLASS_RESET,
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XPM_NODECLASS_MEMIC,
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XPM_NODECLASS_STMIC,
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XPM_NODECLASS_DEVICE,
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XPM_NODECLASS_MAX
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};
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enum pm_device_node_subclass {
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/* Device types */
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XPM_NODESUBCL_DEV_CORE = 1,
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XPM_NODESUBCL_DEV_PERIPH,
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XPM_NODESUBCL_DEV_MEM,
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XPM_NODESUBCL_DEV_SOC,
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XPM_NODESUBCL_DEV_MEM_CTRLR,
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XPM_NODESUBCL_DEV_PHY,
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};
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enum pm_device_node_type {
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/* Device types */
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XPM_NODETYPE_DEV_CORE_PMC = 1,
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XPM_NODETYPE_DEV_CORE_PSM,
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XPM_NODETYPE_DEV_CORE_APU,
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XPM_NODETYPE_DEV_CORE_RPU,
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XPM_NODETYPE_DEV_OCM,
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XPM_NODETYPE_DEV_TCM,
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XPM_NODETYPE_DEV_L2CACHE,
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XPM_NODETYPE_DEV_DDR,
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XPM_NODETYPE_DEV_PERIPH,
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XPM_NODETYPE_DEV_SOC,
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XPM_NODETYPE_DEV_GT,
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};
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/* Device node Indexes */
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enum pm_device_node_idx {
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/* Device nodes */
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XPM_NODEIDX_DEV_MIN,
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/* Processor devices */
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XPM_NODEIDX_DEV_PMC_PROC,
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XPM_NODEIDX_DEV_PSM_PROC,
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XPM_NODEIDX_DEV_ACPU_0,
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XPM_NODEIDX_DEV_ACPU_1,
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XPM_NODEIDX_DEV_RPU0_0,
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XPM_NODEIDX_DEV_RPU0_1,
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/* Memory devices */
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XPM_NODEIDX_DEV_OCM_0,
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XPM_NODEIDX_DEV_OCM_1,
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XPM_NODEIDX_DEV_OCM_2,
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XPM_NODEIDX_DEV_OCM_3,
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XPM_NODEIDX_DEV_TCM_0_A,
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XPM_NODEIDX_DEV_TCM_0_B,
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XPM_NODEIDX_DEV_TCM_1_A,
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XPM_NODEIDX_DEV_TCM_1_B,
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XPM_NODEIDX_DEV_L2_BANK_0,
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XPM_NODEIDX_DEV_DDR_0,
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XPM_NODEIDX_DEV_DDR_1,
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XPM_NODEIDX_DEV_DDR_2,
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XPM_NODEIDX_DEV_DDR_3,
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XPM_NODEIDX_DEV_DDR_4,
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XPM_NODEIDX_DEV_DDR_5,
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XPM_NODEIDX_DEV_DDR_6,
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XPM_NODEIDX_DEV_DDR_7,
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/* LPD Peripheral devices */
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XPM_NODEIDX_DEV_USB_0,
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XPM_NODEIDX_DEV_GEM_0,
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XPM_NODEIDX_DEV_GEM_1,
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XPM_NODEIDX_DEV_SPI_0,
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XPM_NODEIDX_DEV_SPI_1,
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XPM_NODEIDX_DEV_I2C_0,
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XPM_NODEIDX_DEV_I2C_1,
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XPM_NODEIDX_DEV_CAN_FD_0,
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XPM_NODEIDX_DEV_CAN_FD_1,
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XPM_NODEIDX_DEV_UART_0,
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XPM_NODEIDX_DEV_UART_1,
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XPM_NODEIDX_DEV_GPIO,
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XPM_NODEIDX_DEV_TTC_0,
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XPM_NODEIDX_DEV_TTC_1,
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XPM_NODEIDX_DEV_TTC_2,
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XPM_NODEIDX_DEV_TTC_3,
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XPM_NODEIDX_DEV_SWDT_LPD,
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/* FPD Peripheral devices */
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XPM_NODEIDX_DEV_SWDT_FPD,
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/* PMC Peripheral devices */
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XPM_NODEIDX_DEV_OSPI,
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XPM_NODEIDX_DEV_QSPI,
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XPM_NODEIDX_DEV_GPIO_PMC,
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XPM_NODEIDX_DEV_I2C_PMC,
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XPM_NODEIDX_DEV_SDIO_0,
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XPM_NODEIDX_DEV_SDIO_1,
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XPM_NODEIDX_DEV_PL_0,
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XPM_NODEIDX_DEV_PL_1,
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XPM_NODEIDX_DEV_PL_2,
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XPM_NODEIDX_DEV_PL_3,
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XPM_NODEIDX_DEV_RTC,
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XPM_NODEIDX_DEV_ADMA_0,
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XPM_NODEIDX_DEV_ADMA_1,
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XPM_NODEIDX_DEV_ADMA_2,
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XPM_NODEIDX_DEV_ADMA_3,
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XPM_NODEIDX_DEV_ADMA_4,
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XPM_NODEIDX_DEV_ADMA_5,
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XPM_NODEIDX_DEV_ADMA_6,
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XPM_NODEIDX_DEV_ADMA_7,
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XPM_NODEIDX_DEV_IPI_0,
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XPM_NODEIDX_DEV_IPI_1,
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XPM_NODEIDX_DEV_IPI_2,
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XPM_NODEIDX_DEV_IPI_3,
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XPM_NODEIDX_DEV_IPI_4,
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XPM_NODEIDX_DEV_IPI_5,
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XPM_NODEIDX_DEV_IPI_6,
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/* Entire SoC */
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XPM_NODEIDX_DEV_SOC,
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/* DDR memory controllers */
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XPM_NODEIDX_DEV_DDRMC_0,
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XPM_NODEIDX_DEV_DDRMC_1,
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XPM_NODEIDX_DEV_DDRMC_2,
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XPM_NODEIDX_DEV_DDRMC_3,
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/* GT devices */
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XPM_NODEIDX_DEV_GT_0,
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XPM_NODEIDX_DEV_GT_1,
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XPM_NODEIDX_DEV_GT_2,
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XPM_NODEIDX_DEV_GT_3,
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XPM_NODEIDX_DEV_GT_4,
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XPM_NODEIDX_DEV_GT_5,
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XPM_NODEIDX_DEV_GT_6,
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XPM_NODEIDX_DEV_GT_7,
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XPM_NODEIDX_DEV_GT_8,
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XPM_NODEIDX_DEV_GT_9,
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XPM_NODEIDX_DEV_GT_10,
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XPM_NODEIDX_DEV_MAX
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};
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#endif /* PM_NODE_H */
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