Andre Przywara baac5dd4cf plat/tegra: Enable Cortex-A53 erratum 855873 workaround ... The NVidia Tegra 210 SoC contains Cortex-A53 CPUs which are affected by erratum 855873. Enable the workaround that TF provides to fix this erratum. Change-Id: I6cef4ac60ae745e9ce299ee22c93b9d2c4f6c5f2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2017-03-20 10:57:50 +00:00
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plat_psci_handlers.c	Tegra210: assert if afflvl0/1 have incorrect state-ids	2017-03-02 13:02:40 -08:00
plat_secondary.c	Tegra210: lock PMC registers holding CPU vector addresses	2015-07-17 19:06:54 +05:30
plat_setup.c	Tegra: GIC: enable FIQ interrupt handling	2017-02-28 08:50:01 -08:00
platform_t210.mk	plat/tegra: Enable Cortex-A53 erratum 855873 workaround	2017-03-20 10:57:50 +00:00