Soby Mathew f4f1ae777b Demonstrate model for routing IRQs to EL3 ... This patch provides an option to specify a interrupt routing model where non-secure interrupts (IRQs) are routed to EL3 instead of S-EL1. When such an interrupt occurs, the TSPD arranges a return to the normal world after saving any necessary context. The interrupt routing model to route IRQs to EL3 is enabled only during STD SMC processing. Thus the pre-emption of S-EL1 is disabled during Fast SMC and Secure Interrupt processing. A new build option TSPD_ROUTE_NS_INT_EL3 is introduced to change the non secure interrupt target execution level to EL3. Fixes ARM-software/tf-issues#225 Change-Id: Ia1e779fbbb6d627091e665c73fa6315637cfdd32		2015-01-26 15:29:32 +00:00
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services	Increment the PSCI VERSION to 1.0	2015-01-26 12:49:32 +00:00
bl31.h	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00
context.h	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
context_mgmt.h	Optimize EL3 register state stored in cpu_context structure	2014-07-31 10:09:58 +01:00
cpu_data.h	Move bakery algorithm implementation out of coherent memory	2015-01-22 10:57:44 +00:00
interrupt_mgmt.h	Demonstrate model for routing IRQs to EL3	2015-01-26 15:29:32 +00:00
runtime_svc.h	Implement PSCI_FEATURES API	2015-01-26 12:42:45 +00:00