Soby Mathew 683f788fa7 Fix the Cortex-A57 reset handler register usage ... The CPU specific reset handlers no longer have the freedom of using any general purpose register because it is being invoked by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU specific reset handler was overwriting x20 register which was being used by the BL3-1 entry point to save the entry point information. This patch fixes this bug by reworking the register allocation in the Cortex-A57 reset handler to avoid using x20. The patch also explicitly mentions the register clobber list for each of the callee functions invoked by the reset handler Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df		2015-01-30 13:57:57 +00:00
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aarch64	Add support for level specific cache maintenance operations	2014-10-29 17:38:56 +00:00
cpus	Fix the Cortex-A57 reset handler register usage	2015-01-30 13:57:57 +00:00
locks	Move bakery algorithm implementation out of coherent memory	2015-01-22 10:57:44 +00:00
semihosting	Remove extern keyword from function declarations	2014-05-23 12:15:54 +01:00
stdlib	stdlib: add missing features to build PolarSSL	2015-01-28 18:26:59 +00:00