241 lines
7.6 KiB
C
241 lines
7.6 KiB
C
/*
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* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <debug.h>
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#include "../qos_common.h"
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#include "../qos_reg.h"
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#include "qos_init_m3_v11.h"
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#define RCAR_QOS_VERSION "rev.0.17"
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#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
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#define QOSWT_WTEN_ENABLE (0x1U)
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#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 (SL_INIT_SSLOTCLK_M3_11 - 0x5U)
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#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
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#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
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#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
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#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
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#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
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#define WT_BASE_SUB_SLOT_NUM0 (12U)
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#define QOSWT_WTSET0_PERIOD0_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
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#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
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#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
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#define QOSWT_WTSET1_PERIOD1_M3_11 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
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#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
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#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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#include "qos_init_m3_v11_mstat195.h"
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#else
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#include "qos_init_m3_v11_mstat390.h"
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#endif
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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#include "qos_init_m3_v11_qoswt195.h"
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#else
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#include "qos_init_m3_v11_qoswt390.h"
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#endif
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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#endif
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static void dbsc_setting(void)
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{
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uint32_t md = 0;
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/* BUFCAM settings */
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io_write_32(DBSC_DBCAM0CNF1, 0x00043218); /* dbcam0cnf1 */
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io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); /* dbcam0cnf2 */
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io_write_32(DBSC_DBCAM0CNF3, 0x00000000); /* dbcam0cnf3 */
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io_write_32(DBSC_DBSCHCNT0, 0x000F0037); /* dbschcnt0 */
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io_write_32(DBSC_DBSCHSZ0, 0x00000001); /* dbschsz0 */
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io_write_32(DBSC_DBSCHRW0, 0x22421111); /* dbschrw0 */
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md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
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switch (md) {
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case 0x0:
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/* DDR3200 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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break;
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case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
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/* DDR2800 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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break;
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case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
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/* DDR2400 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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break;
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default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
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/* DDR1600 */
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io_write_32(DBSC_SCFCTST2, 0x012F1123);
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break;
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}
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/* QoS Settings */
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io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
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io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
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io_write_32(DBSC_DBSCHQOS02, 0x00000000);
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io_write_32(DBSC_DBSCHQOS03, 0x00000000);
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io_write_32(DBSC_DBSCHQOS40, 0x00000300);
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io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
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io_write_32(DBSC_DBSCHQOS42, 0x00000200);
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io_write_32(DBSC_DBSCHQOS43, 0x00000100);
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io_write_32(DBSC_DBSCHQOS90, 0x00000100);
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io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS93, 0x00000040);
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io_write_32(DBSC_DBSCHQOS120, 0x00000040);
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io_write_32(DBSC_DBSCHQOS121, 0x00000030);
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io_write_32(DBSC_DBSCHQOS122, 0x00000020);
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io_write_32(DBSC_DBSCHQOS123, 0x00000010);
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io_write_32(DBSC_DBSCHQOS130, 0x00000100);
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io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
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io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
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io_write_32(DBSC_DBSCHQOS133, 0x00000040);
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io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
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io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
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io_write_32(DBSC_DBSCHQOS142, 0x00000080);
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io_write_32(DBSC_DBSCHQOS143, 0x00000040);
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io_write_32(DBSC_DBSCHQOS150, 0x00000040);
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io_write_32(DBSC_DBSCHQOS151, 0x00000030);
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io_write_32(DBSC_DBSCHQOS152, 0x00000020);
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io_write_32(DBSC_DBSCHQOS153, 0x00000010);
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}
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void qos_init_m3_v11(void)
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{
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dbsc_setting();
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/* DRAM Split Address mapping */
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#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
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#if RCAR_LSI == RCAR_M3
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#error "Don't set DRAM Split 4ch(M3)"
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#else
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ERROR("DRAM Split 4ch not supported.(M3)");
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panic();
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#endif
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#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
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(RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
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NOTICE("BL2: DRAM Split is 2ch\n");
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io_write_32(AXI_ADSPLCR0, 0x00000000U);
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io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
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| ADSPLCR0_SPLITSEL(0xFFU)
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| ADSPLCR0_AREA(0x1CU)
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| ADSPLCR0_SWP);
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io_write_32(AXI_ADSPLCR2, 0x00001004U);
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io_write_32(AXI_ADSPLCR3, 0x00000000U);
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#else
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NOTICE("BL2: DRAM Split is OFF\n");
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#endif
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#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
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#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
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NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
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#endif
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#if RCAR_REF_INT == RCAR_REF_DEFAULT
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NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
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#else
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NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
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#endif
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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NOTICE("BL2: Periodic Write DQ Training\n");
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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io_write_32(QOSCTRL_RAS, 0x00000044U);
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io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
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io_write_32(QOSCTRL_DANT, 0x0020100AU);
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io_write_32(QOSCTRL_INSFC, 0x06330001U);
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io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
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io_write_32(QOSCTRL_SL_INIT,
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SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
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SL_INIT_SSLOTCLK_M3_11);
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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io_write_32(QOSCTRL_REF_ARS,
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((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 << 16)));
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#else
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io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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{
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
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io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
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io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
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io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
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io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
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}
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
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io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
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qoswt_fix[i]);
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io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
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qoswt_fix[i]);
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}
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for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
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io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
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io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
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}
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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}
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/* 3DG bus Leaf setting */
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io_write_32(GPU_ACT_GRD, 0x00001234U);
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io_write_32(GPU_ACT0, 0x00000000U);
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io_write_32(GPU_ACT1, 0x00000000U);
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io_write_32(GPU_ACT2, 0x00000000U);
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io_write_32(GPU_ACT3, 0x00000000U);
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/* RT bus Leaf setting */
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io_write_32(RT_ACT0, 0x00000000U);
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io_write_32(RT_ACT1, 0x00000000U);
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/* CCI bus Leaf setting */
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io_write_32(CPU_ACT0, 0x00000003U);
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io_write_32(CPU_ACT1, 0x00000003U);
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io_write_32(CPU_ACT2, 0x00000003U);
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io_write_32(CPU_ACT3, 0x00000003U);
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
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/* re-write training setting */
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io_write_32(QOSWT_WTREF,
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((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
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io_write_32(QOSWT_WTSET0,
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((QOSWT_WTSET0_PERIOD0_M3_11 << 16) |
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(QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
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io_write_32(QOSWT_WTSET1,
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((QOSWT_WTSET1_PERIOD1_M3_11 << 16) |
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(QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
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io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
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#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
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io_write_32(QOSCTRL_STATQC, 0x00000001U);
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#else
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NOTICE("BL2: QoS is None\n");
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io_write_32(QOSCTRL_RAEN, 0x00000001U);
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#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
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}
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