316 lines
9.5 KiB
C
316 lines
9.5 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common_def.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <platform.h>
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#include <secure_partition.h>
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#include <string.h>
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#include <types.h>
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#include <xlat_tables_v2.h>
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#include "spm_private.h"
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#include "spm_shim_private.h"
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/* Place translation tables by default along with the ones used by BL31. */
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#endif
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/* Allocate and initialise the translation context for the secure partition. */
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REGISTER_XLAT_CONTEXT2(secure_partition,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
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/* Export a handle on the secure partition translation context */
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xlat_ctx_t *secure_partition_xlat_ctx_handle = &secure_partition_xlat_ctx;
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/* Setup context of the Secure Partition */
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void secure_partition_setup(void)
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{
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VERBOSE("S-EL1/S-EL0 context setup start...\n");
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cpu_context_t *ctx = cm_get_context(SECURE);
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/* Make sure that we got a Secure context. */
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assert(ctx != NULL);
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/* Assert we are in Secure state. */
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assert((read_scr_el3() & SCR_NS_BIT) == 0);
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/* Disable MMU at EL1. */
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disable_mmu_icache_el1();
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/* Invalidate TLBs at EL1. */
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tlbivmalle1();
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dsbish();
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/*
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* General-Purpose registers
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* -------------------------
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*/
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/*
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* X0: Virtual address of a buffer shared between EL3 and Secure EL0.
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* The buffer will be mapped in the Secure EL1 translation regime
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* with Normal IS WBWA attributes and RO data and Execute Never
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* instruction access permissions.
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*
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* X1: Size of the buffer in bytes
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*
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* X2: cookie value (Implementation Defined)
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*
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* X3: cookie value (Implementation Defined)
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*
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* X4 to X30 = 0 (already done by cm_init_my_context())
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*/
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, PLAT_SPM_BUF_BASE);
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, PLAT_SPM_BUF_SIZE);
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, PLAT_SPM_COOKIE_0);
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, PLAT_SPM_COOKIE_1);
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/*
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* SP_EL0: A non-zero value will indicate to the SP that the SPM has
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* initialized the stack pointer for the current CPU through
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* implementation defined means. The value will be 0 otherwise.
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*/
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write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
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PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE);
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/*
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* Setup translation tables
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* ------------------------
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*/
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#if ENABLE_ASSERTIONS
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/* Get max granularity supported by the platform. */
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u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1();
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int tgran64_supported =
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((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN64_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED;
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int tgran16_supported =
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((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN16_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED;
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int tgran4_supported =
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((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) &
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ID_AA64MMFR0_EL1_TGRAN4_MASK) ==
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ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED;
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uintptr_t max_granule_size;
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if (tgran64_supported) {
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max_granule_size = 64 * 1024;
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} else if (tgran16_supported) {
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max_granule_size = 16 * 1024;
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} else {
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assert(tgran4_supported);
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max_granule_size = 4 * 1024;
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}
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VERBOSE("Max translation granule supported: %lu KiB\n",
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max_granule_size / 1024);
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uintptr_t max_granule_size_mask = max_granule_size - 1;
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/* Base must be aligned to the max granularity */
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assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_size_mask) == 0);
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/* Size must be a multiple of the max granularity */
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assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_size_mask) == 0);
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#endif /* ENABLE_ASSERTIONS */
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/* This region contains the exception vectors used at S-EL1. */
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const mmap_region_t sel1_exception_vectors =
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MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START,
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SPM_SHIM_EXCEPTIONS_SIZE,
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MT_CODE | MT_SECURE | MT_PRIVILEGED);
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mmap_add_region_ctx(&secure_partition_xlat_ctx,
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&sel1_exception_vectors);
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mmap_add_ctx(&secure_partition_xlat_ctx,
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plat_get_secure_partition_mmap(NULL));
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init_xlat_tables_ctx(&secure_partition_xlat_ctx);
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/*
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* MMU-related registers
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* ---------------------
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*/
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/* Set attributes in the right indices of the MAIR */
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u_register_t mair_el1 =
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MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX) |
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MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX) |
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MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, mair_el1);
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/* Setup TCR_EL1. */
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u_register_t tcr_ps_bits = tcr_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE);
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u_register_t tcr_el1 =
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/* Size of region addressed by TTBR0_EL1 = 2^(64-T0SZ) bytes. */
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE)) |
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/* Inner and outer WBWA, shareable. */
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TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |
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/* Set the granularity to 4KB. */
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TCR_TG0_4K |
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/* Limit Intermediate Physical Address Size. */
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tcr_ps_bits << TCR_EL1_IPS_SHIFT |
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/* Disable translations using TBBR1_EL1. */
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TCR_EPD1_BIT
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/* The remaining fields related to TBBR1_EL1 are left as zero. */
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;
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tcr_el1 &= ~(
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/* Enable translations using TBBR0_EL1 */
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TCR_EPD0_BIT
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);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, tcr_el1);
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/* Setup SCTLR_EL1 */
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u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
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sctlr_el1 |=
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/*SCTLR_EL1_RES1 |*/
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/* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
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SCTLR_UCI_BIT |
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/* RW regions at xlat regime EL1&0 are forced to be XN. */
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SCTLR_WXN_BIT |
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/* Don't trap to EL1 execution of WFI or WFE at EL0. */
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SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
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/* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
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SCTLR_UCT_BIT |
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/* Don't trap to EL1 execution of DZ ZVA at EL0. */
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SCTLR_DZE_BIT |
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/* Enable SP Alignment check for EL0 */
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SCTLR_SA0_BIT |
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/* Allow cacheable data and instr. accesses to normal memory. */
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SCTLR_C_BIT | SCTLR_I_BIT |
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/* Alignment fault checking enabled when at EL1 and EL0. */
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SCTLR_A_BIT |
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/* Enable MMU. */
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SCTLR_M_BIT
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;
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sctlr_el1 &= ~(
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/* Explicit data accesses at EL0 are little-endian. */
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SCTLR_E0E_BIT |
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/* Accesses to DAIF from EL0 are trapped to EL1. */
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SCTLR_UMA_BIT
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);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
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/* Point TTBR0_EL1 at the tables of the context created for the SP. */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
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(u_register_t)secure_partition_base_xlat_table);
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/*
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* Setup other system registers
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* ----------------------------
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*/
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/* Shim Exception Vector Base Address */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
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SPM_SHIM_EXCEPTIONS_PTR);
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/*
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* FPEN: Forbid the Secure Partition to access FP/SIMD registers.
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* TTA: Enable access to trace registers.
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* ZEN (v8.2): Trap SVE instructions and access to SVE registers.
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*/
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
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CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_ALL));
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/*
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* Prepare information in buffer shared between EL3 and S-EL0
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* ----------------------------------------------------------
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*/
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void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
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/* Copy the boot information into the shared buffer with the SP. */
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assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t)
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<= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
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assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
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const secure_partition_boot_info_t *sp_boot_info =
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plat_get_secure_partition_boot_info(NULL);
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assert(sp_boot_info != NULL);
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memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
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sizeof(secure_partition_boot_info_t));
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/* Pointer to the MP information from the platform port. */
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secure_partition_mp_info_t *sp_mp_info =
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((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
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assert(sp_mp_info != NULL);
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/*
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* Point the shared buffer MP information pointer to where the info will
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* be populated, just after the boot info.
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*/
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((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info =
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(secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr
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+ sizeof(secure_partition_boot_info_t));
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/*
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* Update the shared buffer pointer to where the MP information for the
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* payload will be populated
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*/
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shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
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/*
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* Copy the cpu information into the shared buffer area after the boot
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* information.
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*/
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assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
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assert((uintptr_t)shared_buf_ptr
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<= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE -
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(sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
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memcpy(shared_buf_ptr, (const void *) sp_mp_info,
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sp_boot_info->num_cpus * sizeof(*sp_mp_info));
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/*
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* Calculate the linear indices of cores in boot information for the
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* secure partition and flag the primary CPU
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*/
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sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr;
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for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
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u_register_t mpidr = sp_mp_info[index].mpidr;
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sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr);
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if (plat_my_core_pos() == sp_mp_info[index].linear_id)
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sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU;
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}
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VERBOSE("S-EL1/S-EL0 context setup end.\n");
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}
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