49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <gicv2.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <stm32mp1_private.h>
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*****************************************************************************/
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static const interrupt_prop_t stm32mp1_interrupt_props[] = {
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PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
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PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
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};
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static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
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static const gicv2_driver_data_t platform_gic_data = {
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.gicd_base = STM32MP1_GICD_BASE,
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.gicc_base = STM32MP1_GICC_BASE,
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.interrupt_props = stm32mp1_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
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.target_masks = target_mask_array,
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.target_masks_num = ARRAY_SIZE(target_mask_array),
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};
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void stm32mp1_gic_init(void)
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{
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gicv2_driver_init(&platform_gic_data);
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gicv2_distif_init();
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stm32mp1_gic_pcpu_init();
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}
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void stm32mp1_gic_pcpu_init(void)
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{
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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gicv2_cpuif_enable();
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}
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