arm-trusted-firmware/lib/cpus/aarch64
Dimitris Papastamos bd5a76ac7c cpulib: Add ISBs or comment why they are unneeded
Change-Id: I18a41bb9fedda635c3c002a7f112578808410ef6
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-06-19 10:34:51 +01:00
..
aem_generic.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a35.S Use SPDX license identifiers 2017-05-03 09:39:28 +01:00
cortex_a53.S Check presence of fix for errata 835769 in Cortex-A53 2018-04-12 12:12:56 +01:00
cortex_a55.S Fix order of #includes 2017-07-12 14:45:31 +01:00
cortex_a57.S cpulib: Add ISBs or comment why they are unneeded 2018-06-19 10:34:51 +01:00
cortex_a72.S cpulib: Add ISBs or comment why they are unneeded 2018-06-19 10:34:51 +01:00
cortex_a73.S cpulib: Add ISBs or comment why they are unneeded 2018-06-19 10:34:51 +01:00
cortex_a75.S cpulib: Add ISBs or comment why they are unneeded 2018-06-19 10:34:51 +01:00
cortex_a75_pubsub.c MISRA fixes for Cortex A75 AMU implementation 2018-02-27 13:28:41 +00:00
cortex_a76.S Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76 2018-06-08 11:46:31 +01:00
cortex_ares.S Implement Cortex-Ares 1043202 erratum workaround 2018-06-08 11:46:31 +01:00
cortex_ares_pubsub.c Add AMU support for Cortex-Ares 2018-06-08 11:46:31 +01:00
cpu_helpers.S Add support for dynamic mitigation for CVE-2018-3639 2018-05-23 12:45:48 +01:00
cpuamu.c Fix MISRA Rule 5.7 Part 1 2018-06-12 13:21:36 +01:00
cpuamu_helpers.S Factor out CPU AMU helpers 2018-02-27 13:28:41 +00:00
denver.S Workaround for CVE-2017-5715 on NVIDIA Denver CPUs 2018-05-15 15:53:50 -07:00
wa_cve_2017_5715_bpiall.S Rename symbols and files relating to CVE-2017-5715 2018-05-23 12:45:48 +01:00
wa_cve_2017_5715_mmu.S Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32 2018-06-07 14:34:45 +01:00