72 lines
1.8 KiB
C
72 lines
1.8 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include "fpga_private.h"
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#include <platform_def.h>
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static unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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int i;
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/*
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* The highest level is the system level. The next level is constituted
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* by clusters and then cores in clusters.
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*
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* This description of the power domain topology is aligned with the CPU
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* indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
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* APIs.
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*/
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fpga_power_domain_tree_desc[0] = 1;
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fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
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for (i = 0; i < FPGA_MAX_CLUSTER_COUNT; i++) {
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fpga_power_domain_tree_desc[i + 2] = FPGA_MAX_CPUS_PER_CLUSTER;
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}
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return fpga_power_domain_tree_desc;
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}
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id, thread_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
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return -1;
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}
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if (mpidr & MPIDR_MT_MASK) {
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thread_id = MPIDR_AFFLVL0_VAL(mpidr);
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} else {
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thread_id = 0;
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}
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cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
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cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
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if (cluster_id >= FPGA_MAX_CLUSTER_COUNT) {
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return -1;
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} else if (cpu_id >= FPGA_MAX_CPUS_PER_CLUSTER) {
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return -1;
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} else if (thread_id >= FPGA_MAX_PE_PER_CPU) {
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return -1;
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}
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/*
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* The image running on the FPGA may or may not implement multithreading,
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* and it shouldn't be assumed this is consistent across all CPUs.
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* This ensures that any passed mpidr values reflect the status of the
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* primary CPU's MT bit.
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*/
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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/* Calculate the correct core, catering for multi-threaded images */
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return (int) plat_fpga_calc_core_pos(mpidr);
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}
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