72 lines
1.8 KiB
ArmAsm
72 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2022, Google LLC. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cortex_x1.h>
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#include <cpu_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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func cortex_x1_reset_func
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ret
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endfunc cortex_x1_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_x1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
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msr CORTEX_X1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_x1_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex X1. Must follow AAPCS.
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*/
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func cortex_x1_errata_report
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ret
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endfunc cortex_x1_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex X1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x1_regs, "aS"
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cortex_x1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x1_cpu_reg_dump
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adr x6, cortex_x1_regs
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mrs x8, CORTEX_X1_CPUECTLR_EL1
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ret
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endfunc cortex_x1_cpu_reg_dump
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declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \
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cortex_x1_reset_func, \
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cortex_x1_core_pwr_dwn
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