142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef _SOC_H
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#define _SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include <dcfg_lsch3.h>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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#define NUM_DRAM_REGIONS 3
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x2080000000
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#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */
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#define NXP_DRAM2_ADDR 0x6000000000
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#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */
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/*DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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#define DDR_PLL_FIX
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#define NXP_DDR_PHY1_ADDR 0x01400000
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#define NXP_DDR_PHY2_ADDR 0x01600000
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#if defined(IMAGE_BL31)
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#define LS_SYS_TIMCTL_BASE 0x2890000
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#ifdef LS_SYS_TIMCTL_BASE
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#define PLAT_LS_NSTIMER_FRAME_ID 0
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#define LS_CONFIG_CNTACR 1
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#endif
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#endif
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/* Start: Macros used by soc.c: get_boot_dev */
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#define PORSR1_RCW_MASK 0x07800000
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#define PORSR1_RCW_SHIFT 23
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#define SDHC1_VAL 0x8
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#define SDHC2_VAL 0x9
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#define I2C1_VAL 0xa
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#define FLEXSPI_NAND2K_VAL 0xc
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#define FLEXSPI_NAND4K_VAL 0xd
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#define FLEXSPI_NOR 0xf
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/* End: Macros used by soc.c: get_boot_dev */
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/* SVR Definition (not include major and minor rev) */
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#define SVR_LX2160A 0x873601
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#define SVR_LX2120A 0x873621
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#define SVR_LX2080A 0x873603
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/* Number of cores in platform */
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/* Used by common code for array initialization */
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#define NUMBER_OF_CLUSTERS 8
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#define CORES_PER_CLUSTER 2
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#define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER
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/*
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* Required LS standard platform porting definitions
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* for CCN-508
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*/
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#define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0
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#define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER 2
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#define NXP_UART_CLK_DIVIDER 4
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/* Start: Macros used by lx2160a.S */
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#define MPIDR_AFFINITY0_MASK 0x00FF
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#define MPIDR_AFFINITY1_MASK 0xFF00
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#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000
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#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000
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#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000
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#define CPUECTLR_RET_8CLK 0x2
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#define OSDLR_EL1_DLK_LOCK 0x1
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#define CNTP_CTL_EL0_EN 0x1
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#define CNTP_CTL_EL0_IMASK 0x2
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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/* End: Macros used by lx2160a.S */
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/* Start: Macros used by lib/psci files */
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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/* End: Macros used by lib/psci files */
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/* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*
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* CACHE_WRITEBACK_GRANULE is defined in soc.def
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*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef WDOG_RESET_FLAG
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#define WDOG_RESET_FLAG DEFAULT_SET_VALUE
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#endif
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#ifndef WARM_BOOT_SUCCESS
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#define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE
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#endif
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#ifndef __ASSEMBLER__
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void set_base_freq_CNTFID0(void);
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void soc_init_start(void);
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void soc_init_finish(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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void _set_platform_security(void);
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#endif
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#endif /* _SOC_H */
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