507 lines
15 KiB
C
507 lines
15 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <memctrl_v2.h>
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#include <platform_def.h>
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#include <smmu.h>
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#include <string.h>
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#include <tegra_private.h>
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typedef struct smmu_regs {
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uint32_t reg;
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uint32_t val;
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} smmu_regs_t;
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#define mc_make_sid_override_cfg(name) \
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{ \
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.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
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.val = 0x00000000, \
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}
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#define mc_make_sid_security_cfg(name) \
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{ \
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.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_SECURITY_CFG_ ## name, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_sec_cfg(name) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
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.val = 0x00000000, \
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}
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/*
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* On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
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* is 0x400. So, add it to register address
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*/
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#define smmu_make_gnsr0_nsec_cfg(name) \
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{ \
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.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_smr_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_s2cr_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr1_cbar_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr1_cba2r_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
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.val = 0x00000000, \
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}
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#define make_smmu_cb_cfg(name, n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
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+ SMMU_CBn_ ## name, \
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.val = 0x00000000, \
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}
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#define smmu_make_smrg_group(n) \
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smmu_make_gnsr0_smr_cfg(n), \
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smmu_make_gnsr0_s2cr_cfg(n), \
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smmu_make_gnsr1_cbar_cfg(n), \
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smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */
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#define smmu_make_cb_group(n) \
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make_smmu_cb_cfg(SCTLR, n), \
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make_smmu_cb_cfg(TCR2, n), \
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make_smmu_cb_cfg(TTBR0_LO, n), \
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make_smmu_cb_cfg(TTBR0_HI, n), \
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make_smmu_cb_cfg(TCR, n), \
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make_smmu_cb_cfg(PRRR_MAIR0, n),\
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make_smmu_cb_cfg(FSR, n), \
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make_smmu_cb_cfg(FAR_LO, n), \
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make_smmu_cb_cfg(FAR_HI, n), \
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make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */
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#define smmu_bypass_cfg \
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{ \
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.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
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.val = 0x00000000, \
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}
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#define _START_OF_TABLE_ \
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{ \
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.reg = 0xCAFE05C7, \
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.val = 0x00000000, \
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}
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#define _END_OF_TABLE_ \
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{ \
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.reg = 0xFFFFFFFF, \
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.val = 0xFFFFFFFF, \
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}
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static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
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_START_OF_TABLE_,
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mc_make_sid_security_cfg(SCEW),
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mc_make_sid_security_cfg(AFIR),
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mc_make_sid_security_cfg(NVDISPLAYR1),
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mc_make_sid_security_cfg(XUSB_DEVR),
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mc_make_sid_security_cfg(VICSRD1),
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mc_make_sid_security_cfg(NVENCSWR),
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mc_make_sid_security_cfg(TSECSRDB),
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mc_make_sid_security_cfg(AXISW),
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mc_make_sid_security_cfg(SDMMCWAB),
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mc_make_sid_security_cfg(AONDMAW),
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mc_make_sid_security_cfg(GPUSWR2),
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mc_make_sid_security_cfg(SATAW),
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mc_make_sid_security_cfg(UFSHCW),
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mc_make_sid_security_cfg(AFIW),
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mc_make_sid_security_cfg(SDMMCR),
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mc_make_sid_security_cfg(SCEDMAW),
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mc_make_sid_security_cfg(UFSHCR),
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mc_make_sid_security_cfg(SDMMCWAA),
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mc_make_sid_security_cfg(APEDMAW),
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mc_make_sid_security_cfg(SESWR),
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mc_make_sid_security_cfg(MPCORER),
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mc_make_sid_security_cfg(PTCR),
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mc_make_sid_security_cfg(BPMPW),
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mc_make_sid_security_cfg(ETRW),
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mc_make_sid_security_cfg(GPUSRD),
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mc_make_sid_security_cfg(VICSWR),
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mc_make_sid_security_cfg(SCEDMAR),
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mc_make_sid_security_cfg(HDAW),
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mc_make_sid_security_cfg(ISPWA),
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mc_make_sid_security_cfg(EQOSW),
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mc_make_sid_security_cfg(XUSB_HOSTW),
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mc_make_sid_security_cfg(TSECSWR),
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mc_make_sid_security_cfg(SDMMCRAA),
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mc_make_sid_security_cfg(APER),
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mc_make_sid_security_cfg(VIW),
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mc_make_sid_security_cfg(APEW),
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mc_make_sid_security_cfg(AXISR),
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mc_make_sid_security_cfg(SDMMCW),
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mc_make_sid_security_cfg(BPMPDMAW),
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mc_make_sid_security_cfg(ISPRA),
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mc_make_sid_security_cfg(NVDECSWR),
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mc_make_sid_security_cfg(XUSB_DEVW),
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mc_make_sid_security_cfg(NVDECSRD),
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mc_make_sid_security_cfg(MPCOREW),
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mc_make_sid_security_cfg(NVDISPLAYR),
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mc_make_sid_security_cfg(BPMPDMAR),
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mc_make_sid_security_cfg(NVJPGSWR),
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mc_make_sid_security_cfg(NVDECSRD1),
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mc_make_sid_security_cfg(TSECSRD),
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mc_make_sid_security_cfg(NVJPGSRD),
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mc_make_sid_security_cfg(SDMMCWA),
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mc_make_sid_security_cfg(SCER),
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mc_make_sid_security_cfg(XUSB_HOSTR),
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mc_make_sid_security_cfg(VICSRD),
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mc_make_sid_security_cfg(AONDMAR),
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mc_make_sid_security_cfg(AONW),
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mc_make_sid_security_cfg(SDMMCRA),
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mc_make_sid_security_cfg(HOST1XDMAR),
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mc_make_sid_security_cfg(EQOSR),
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mc_make_sid_security_cfg(SATAR),
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mc_make_sid_security_cfg(BPMPR),
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mc_make_sid_security_cfg(HDAR),
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mc_make_sid_security_cfg(SDMMCRAB),
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mc_make_sid_security_cfg(ETRR),
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mc_make_sid_security_cfg(AONR),
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mc_make_sid_security_cfg(APEDMAR),
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mc_make_sid_security_cfg(SESRD),
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mc_make_sid_security_cfg(NVENCSRD),
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mc_make_sid_security_cfg(GPUSWR),
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mc_make_sid_security_cfg(TSECSWRB),
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mc_make_sid_security_cfg(ISPWB),
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mc_make_sid_security_cfg(GPUSRD2),
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mc_make_sid_override_cfg(APER),
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mc_make_sid_override_cfg(VICSRD),
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mc_make_sid_override_cfg(NVENCSRD),
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mc_make_sid_override_cfg(NVJPGSWR),
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mc_make_sid_override_cfg(AONW),
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mc_make_sid_override_cfg(BPMPR),
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mc_make_sid_override_cfg(BPMPW),
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mc_make_sid_override_cfg(HDAW),
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mc_make_sid_override_cfg(NVDISPLAYR1),
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mc_make_sid_override_cfg(APEDMAR),
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mc_make_sid_override_cfg(AFIR),
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mc_make_sid_override_cfg(AXISR),
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mc_make_sid_override_cfg(VICSRD1),
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mc_make_sid_override_cfg(TSECSRD),
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mc_make_sid_override_cfg(BPMPDMAW),
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mc_make_sid_override_cfg(MPCOREW),
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mc_make_sid_override_cfg(XUSB_HOSTR),
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mc_make_sid_override_cfg(GPUSWR),
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mc_make_sid_override_cfg(XUSB_DEVR),
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mc_make_sid_override_cfg(UFSHCW),
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mc_make_sid_override_cfg(XUSB_HOSTW),
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mc_make_sid_override_cfg(SDMMCWAB),
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mc_make_sid_override_cfg(SATAW),
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mc_make_sid_override_cfg(SCEDMAR),
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mc_make_sid_override_cfg(HOST1XDMAR),
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mc_make_sid_override_cfg(SDMMCWA),
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mc_make_sid_override_cfg(APEDMAW),
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mc_make_sid_override_cfg(SESWR),
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mc_make_sid_override_cfg(AXISW),
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mc_make_sid_override_cfg(AONDMAW),
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mc_make_sid_override_cfg(TSECSWRB),
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mc_make_sid_override_cfg(MPCORER),
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mc_make_sid_override_cfg(ISPWB),
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mc_make_sid_override_cfg(AONR),
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mc_make_sid_override_cfg(BPMPDMAR),
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mc_make_sid_override_cfg(HDAR),
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mc_make_sid_override_cfg(SDMMCRA),
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mc_make_sid_override_cfg(ETRW),
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mc_make_sid_override_cfg(GPUSWR2),
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mc_make_sid_override_cfg(EQOSR),
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mc_make_sid_override_cfg(TSECSWR),
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mc_make_sid_override_cfg(ETRR),
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mc_make_sid_override_cfg(NVDECSRD),
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mc_make_sid_override_cfg(TSECSRDB),
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mc_make_sid_override_cfg(SDMMCRAA),
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mc_make_sid_override_cfg(NVDECSRD1),
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mc_make_sid_override_cfg(SDMMCR),
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mc_make_sid_override_cfg(NVJPGSRD),
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mc_make_sid_override_cfg(SCEDMAW),
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mc_make_sid_override_cfg(SDMMCWAA),
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mc_make_sid_override_cfg(APEW),
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mc_make_sid_override_cfg(AONDMAR),
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mc_make_sid_override_cfg(PTCR),
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mc_make_sid_override_cfg(SCER),
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mc_make_sid_override_cfg(ISPRA),
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mc_make_sid_override_cfg(ISPWA),
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mc_make_sid_override_cfg(VICSWR),
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mc_make_sid_override_cfg(SESRD),
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mc_make_sid_override_cfg(SDMMCW),
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mc_make_sid_override_cfg(SDMMCRAB),
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mc_make_sid_override_cfg(EQOSW),
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mc_make_sid_override_cfg(GPUSRD2),
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mc_make_sid_override_cfg(SCEW),
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mc_make_sid_override_cfg(GPUSRD),
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mc_make_sid_override_cfg(NVDECSWR),
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mc_make_sid_override_cfg(XUSB_DEVW),
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mc_make_sid_override_cfg(SATAR),
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mc_make_sid_override_cfg(NVDISPLAYR),
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mc_make_sid_override_cfg(VIW),
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mc_make_sid_override_cfg(UFSHCR),
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mc_make_sid_override_cfg(NVENCSWR),
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mc_make_sid_override_cfg(AFIW),
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smmu_make_gnsr0_nsec_cfg(CR0),
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smmu_make_gnsr0_sec_cfg(IDR0),
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smmu_make_gnsr0_sec_cfg(IDR1),
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smmu_make_gnsr0_sec_cfg(IDR2),
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smmu_make_gnsr0_nsec_cfg(GFSR),
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smmu_make_gnsr0_nsec_cfg(GFSYNR0),
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smmu_make_gnsr0_nsec_cfg(GFSYNR1),
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smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
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smmu_make_gnsr0_nsec_cfg(PIDR2),
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smmu_make_smrg_group(0),
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smmu_make_smrg_group(1),
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smmu_make_smrg_group(2),
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smmu_make_smrg_group(3),
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smmu_make_smrg_group(4),
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smmu_make_smrg_group(5),
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smmu_make_smrg_group(6),
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smmu_make_smrg_group(7),
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smmu_make_smrg_group(8),
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smmu_make_smrg_group(9),
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smmu_make_smrg_group(10),
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smmu_make_smrg_group(11),
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smmu_make_smrg_group(12),
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smmu_make_smrg_group(13),
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smmu_make_smrg_group(14),
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smmu_make_smrg_group(15),
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smmu_make_smrg_group(16),
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smmu_make_smrg_group(17),
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smmu_make_smrg_group(18),
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smmu_make_smrg_group(19),
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smmu_make_smrg_group(20),
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smmu_make_smrg_group(21),
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smmu_make_smrg_group(22),
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smmu_make_smrg_group(23),
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smmu_make_smrg_group(24),
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smmu_make_smrg_group(25),
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smmu_make_smrg_group(26),
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smmu_make_smrg_group(27),
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smmu_make_smrg_group(28),
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smmu_make_smrg_group(29),
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smmu_make_smrg_group(30),
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smmu_make_smrg_group(31),
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smmu_make_smrg_group(32),
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smmu_make_smrg_group(33),
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smmu_make_smrg_group(34),
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smmu_make_smrg_group(35),
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smmu_make_smrg_group(36),
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smmu_make_smrg_group(37),
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smmu_make_smrg_group(38),
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smmu_make_smrg_group(39),
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smmu_make_smrg_group(40),
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smmu_make_smrg_group(41),
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smmu_make_smrg_group(42),
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smmu_make_smrg_group(43),
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smmu_make_smrg_group(44),
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smmu_make_smrg_group(45),
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smmu_make_smrg_group(46),
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smmu_make_smrg_group(47),
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smmu_make_smrg_group(48),
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smmu_make_smrg_group(49),
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smmu_make_smrg_group(50),
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smmu_make_smrg_group(51),
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smmu_make_smrg_group(52),
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smmu_make_smrg_group(53),
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smmu_make_smrg_group(54),
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smmu_make_smrg_group(55),
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smmu_make_smrg_group(56),
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smmu_make_smrg_group(57),
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smmu_make_smrg_group(58),
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smmu_make_smrg_group(59),
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smmu_make_smrg_group(60),
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smmu_make_smrg_group(61),
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smmu_make_smrg_group(62),
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smmu_make_smrg_group(63),
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smmu_make_cb_group(0),
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smmu_make_cb_group(1),
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smmu_make_cb_group(2),
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smmu_make_cb_group(3),
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smmu_make_cb_group(4),
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smmu_make_cb_group(5),
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smmu_make_cb_group(6),
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smmu_make_cb_group(7),
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smmu_make_cb_group(8),
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smmu_make_cb_group(9),
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smmu_make_cb_group(10),
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smmu_make_cb_group(11),
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smmu_make_cb_group(12),
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smmu_make_cb_group(13),
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smmu_make_cb_group(14),
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smmu_make_cb_group(15),
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smmu_make_cb_group(16),
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smmu_make_cb_group(17),
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smmu_make_cb_group(18),
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smmu_make_cb_group(19),
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smmu_make_cb_group(20),
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smmu_make_cb_group(21),
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smmu_make_cb_group(22),
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smmu_make_cb_group(23),
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smmu_make_cb_group(24),
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smmu_make_cb_group(25),
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smmu_make_cb_group(26),
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smmu_make_cb_group(27),
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smmu_make_cb_group(28),
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smmu_make_cb_group(29),
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smmu_make_cb_group(30),
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smmu_make_cb_group(31),
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smmu_make_cb_group(32),
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smmu_make_cb_group(33),
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smmu_make_cb_group(34),
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smmu_make_cb_group(35),
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smmu_make_cb_group(36),
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smmu_make_cb_group(37),
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smmu_make_cb_group(38),
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smmu_make_cb_group(39),
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smmu_make_cb_group(40),
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smmu_make_cb_group(41),
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smmu_make_cb_group(42),
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smmu_make_cb_group(43),
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smmu_make_cb_group(44),
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smmu_make_cb_group(45),
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smmu_make_cb_group(46),
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smmu_make_cb_group(47),
|
|
smmu_make_cb_group(48),
|
|
smmu_make_cb_group(49),
|
|
smmu_make_cb_group(50),
|
|
smmu_make_cb_group(51),
|
|
smmu_make_cb_group(52),
|
|
smmu_make_cb_group(53),
|
|
smmu_make_cb_group(54),
|
|
smmu_make_cb_group(55),
|
|
smmu_make_cb_group(56),
|
|
smmu_make_cb_group(57),
|
|
smmu_make_cb_group(58),
|
|
smmu_make_cb_group(59),
|
|
smmu_make_cb_group(60),
|
|
smmu_make_cb_group(61),
|
|
smmu_make_cb_group(62),
|
|
smmu_make_cb_group(63),
|
|
smmu_bypass_cfg, /* TBU settings */
|
|
_END_OF_TABLE_,
|
|
};
|
|
|
|
/*
|
|
* Save SMMU settings before "System Suspend" to TZDRAM
|
|
*/
|
|
void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
|
|
{
|
|
uint32_t i;
|
|
#if DEBUG
|
|
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
|
|
uint64_t tzdram_base = params_from_bl2->tzdram_base;
|
|
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
|
|
uint32_t reg_id1, pgshift, cb_size;
|
|
|
|
/* sanity check SMMU settings c*/
|
|
reg_id1 = mmio_read_32((TEGRA_SMMU_BASE + SMMU_GNSR0_IDR1));
|
|
pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
|
|
cb_size = (2 << pgshift) * \
|
|
(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
|
|
|
|
assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
|
|
#endif
|
|
|
|
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
|
|
|
|
/* index of _END_OF_TABLE_ */
|
|
smmu_ctx_regs[0].val = ARRAY_SIZE(smmu_ctx_regs) - 1;
|
|
|
|
/* save SMMU register values */
|
|
for (i = 1; i < ARRAY_SIZE(smmu_ctx_regs) - 1; i++)
|
|
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
|
|
|
|
/* Save SMMU config settings */
|
|
memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
|
|
sizeof(smmu_ctx_regs));
|
|
|
|
/* save the SMMU table address */
|
|
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
|
|
(uint32_t)smmu_ctx_addr);
|
|
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
|
|
(uint32_t)(smmu_ctx_addr >> 32));
|
|
}
|
|
|
|
#define SMMU_NUM_CONTEXTS 64
|
|
#define SMMU_CONTEXT_BANK_MAX_IDX 64
|
|
|
|
/*
|
|
* Init SMMU during boot or "System Suspend" exit
|
|
*/
|
|
void tegra_smmu_init(void)
|
|
{
|
|
uint32_t val, i, ctx_base;
|
|
|
|
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
|
|
val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
|
|
val |= SMMU_GSR0_PGSIZE_64K;
|
|
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
|
|
tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
|
|
|
|
/* reset CACHE LOCK bit for NS Aux. Config. Register */
|
|
val = tegra_smmu_read_32(SMMU_GNSR_ACR);
|
|
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
|
|
tegra_smmu_write_32(SMMU_GNSR_ACR, val);
|
|
|
|
/* disable TCU prefetch for all contexts */
|
|
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + SMMU_CBn_ACTLR;
|
|
for (i = 0; i < SMMU_CONTEXT_BANK_MAX_IDX; i++) {
|
|
val = tegra_smmu_read_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i));
|
|
val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
|
|
tegra_smmu_write_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i), val);
|
|
}
|
|
|
|
/* set CACHE LOCK bit for NS Aux. Config. Register */
|
|
val = tegra_smmu_read_32(SMMU_GNSR_ACR);
|
|
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
|
|
tegra_smmu_write_32(SMMU_GNSR_ACR, val);
|
|
|
|
/* set CACHE LOCK bit for S Aux. Config. Register */
|
|
val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
|
|
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
|
|
tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
|
|
}
|