131 lines
3.3 KiB
ArmAsm
131 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a77.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1800714.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1800714_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1800714
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cbz x0, 1f
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/* Disable allocation of splintered pages in the L2 TLB */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1800714_wa
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func check_errata_1800714
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1800714
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a77_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A77_1800714
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mov x0, x18
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bl errata_a77_1800714_wa
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#endif
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ret x19
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endfunc cortex_a77_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a77_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A77_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a77_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A77. Must follow AAPCS.
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*/
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func cortex_a77_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A77_1800714, cortex_a77, 1800714
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a77_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex-A77 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a77_regs, "aS"
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cortex_a77_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a77_cpu_reg_dump
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adr x6, cortex_a77_regs
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mrs x8, CORTEX_A77_CPUECTLR_EL1
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ret
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endfunc cortex_a77_cpu_reg_dump
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declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
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cortex_a77_reset_func, \
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cortex_a77_core_pwr_dwn
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