54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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/************************************************************
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* For R-class everything is in secure world.
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* Prepare the CPU system registers for first entry into EL1
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************************************************************/
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void cm_prepare_el2_exit(void)
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{
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uint64_t hcr_el2 = 0U;
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/*
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* The use of ARMv8.3 pointer authentication (PAuth) is governed
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* by fields in HCR_EL2, which trigger a 'trap to EL2' if not
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* enabled. This register initialized at boot up, update PAuth
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* bits.
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*
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* HCR_API_BIT: Set to one to disable traps to EL2 if lower ELs
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* access PAuth registers
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*
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* HCR_APK_BIT: Set to one to disable traps to EL2 if lower ELs
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* access PAuth instructions
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*/
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hcr_el2 = read_hcr_el2();
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write_hcr_el2(hcr_el2 | HCR_API_BIT | HCR_APK_BIT);
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/*
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* Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN
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* on reset and are set to zero except for field(s) listed below.
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*
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* CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to EL2
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* if lower ELs accesses to the physical timer registers.
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*
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* CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to EL2
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* if lower ELs access to the physical counter registers.
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*/
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write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
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/*
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* On Armv8-R, the EL1&0 memory system architecture is configurable
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* as a VMSA or PMSA. All the fields architecturally UNKNOWN on reset
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* and are set to zero except for field listed below.
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*
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* VCTR_EL2.MSA: Set to one to ensure the VMSA is enabled so that
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* rich OS can boot.
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*/
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write_vtcr_el2(VTCR_RESET_VAL | VTCR_EL2_MSA);
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}
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