28 lines
864 B
C
28 lines
864 B
C
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/utils.h>
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#include <plat/arm/common/plat_arm.h>
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void bl2_platform_setup(void)
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{
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#ifdef TARGET_PLATFORM_SOC
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/*
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* Morello platform supports RDIMMs with ECC capability. To use the ECC
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* capability, the entire DDR memory space has to be zeroed out before
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* enabling the ECC bits in DMC-Bing.
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* Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage,
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* as BL33 binary cannot be copied to DDR memory before enabling ECC.
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* Rest of the DDR memory space is zeroed out during BL31 stage.
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*/
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INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n");
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE);
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#endif
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arm_bl2_platform_setup();
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}
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