Andrew Thoelke 74f99d24a5 Limit BL3-1 read/write access to SRAM ... At present BL3-1 has access to all of the SRAM, including regions that are mapped as read-only and non-cacheable by other firmware images. This patch restricts BL3-1 to only be able to read/write from memory used for its own data sections Change-Id: I26cda1b9ba803d91a9eacda768f3ce7032c6db94		2014-05-22 13:44:47 +01:00
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aarch64	Reserve some DDR DRAM for secure use on FVP platforms	2014-05-22 12:31:17 +01:00
drivers/pwrc	Reduce deep nesting of header files	2014-05-06 13:57:48 +01:00
include	Rework BL3-1 unhandled exception handling and reporting	2014-05-16 14:51:00 +01:00
bl1_plat_setup.c	Add support for BL3-1 as a reset vector	2014-05-21 16:46:29 +01:00
bl2_plat_setup.c	Merge pull request #98 from jcastillo-arm:jc/tf-issues/149	2014-05-22 12:58:41 +01:00
bl31_plat_setup.c	Limit BL3-1 read/write access to SRAM	2014-05-22 13:44:47 +01:00
bl32_plat_setup.c	Merge pull request #79 from achingupta:ag/tf-issues#104	2014-05-22 13:10:15 +01:00
plat_gic.c	Introduce platform api to access an ARM GIC	2014-05-19 13:10:49 +01:00
plat_io_storage.c	Remove variables from .data section	2014-05-06 17:55:38 +01:00
plat_pm.c	Add support for BL3-1 as a reset vector	2014-05-21 16:46:29 +01:00
plat_security.c	Reserve some DDR DRAM for secure use on FVP platforms	2014-05-22 12:31:17 +01:00
plat_topology.c	Reduce deep nesting of header files	2014-05-06 13:57:48 +01:00
platform.h	Merge pull request #79 from achingupta:ag/tf-issues#104	2014-05-22 13:10:15 +01:00
platform.mk	Merge pull request #79 from achingupta:ag/tf-issues#104	2014-05-22 13:10:15 +01:00