Jeenu Viswambharan 17e84eedb2 GIC: Fix setting interrupt configuration ... - Interrupt configuration is a 2-bit field, so the field shift has to be double that of the bit number. - Interrupt configuration (level- or edge-trigger) is specified in the MSB of the field, not LSB. Fixes applied to both GICv2 and GICv3 drivers. Fixes ARM-software/tf-issues#570 Change-Id: Ia6ae6ed9ba9fb0e3eb0f921a833af48e365ba359 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2018-03-26 09:45:48 +01:00
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gic_common.c	GIC: Fix setting interrupt configuration	2018-03-26 09:45:48 +01:00
gic_common_private.h	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00