52 lines
993 B
Plaintext
52 lines
993 B
Plaintext
/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 0x4001300>;
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max-size = <0x1800>;
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id = <TB_FW_CONFIG_ID>;
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};
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hw-config {
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load-address = <0x0 0x82000000>;
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max-size = <0x01000000>;
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id = <HW_CONFIG_ID>;
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};
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/*
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* Load SoC and TOS firmware configs at the base of
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* non shared SRAM. The runtime checks ensure we don't
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* overlap BL2, BL31 or BL32. The NT firmware config
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* is loaded at base of DRAM.
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*/
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soc_fw-config {
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load-address = <0x0 0x04001300>;
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max-size = <0x200>;
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id = <SOC_FW_CONFIG_ID>;
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};
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tos_fw-config {
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load-address = <0x0 0x04001500>;
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max-size = <0xB00>;
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id = <TOS_FW_CONFIG_ID>;
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};
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nt_fw-config {
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load-address = <0x0 0x80000000>;
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max-size = <0x200>;
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id = <NT_FW_CONFIG_ID>;
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};
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};
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};
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