109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_acle.h>
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#include <assert.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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#include <lib/smccc.h>
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#include <services/trng_svc.h>
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#include <smccc_helpers.h>
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#include <plat/common/platform.h>
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#define NSAMPLE_CLOCKS 1 /* min 1 cycle, max 231 cycles */
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#define NRETRIES 5
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/* initialised to false */
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static bool juno_trng_initialized;
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static bool output_valid(void)
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{
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int i;
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for (i = 0; i < NRETRIES; i++) {
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uint32_t val;
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val = mmio_read_32(TRNG_BASE + TRNG_STATUS);
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if (val & 1U)
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return true;
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}
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return false; /* No output data available. */
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}
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DEFINE_SVC_UUID2(_plat_trng_uuid,
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0x23523c58, 0x7448, 0x4083, 0x9d, 0x16,
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0xe3, 0xfa, 0xb9, 0xf1, 0x73, 0xbc
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);
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uuid_t plat_trng_uuid;
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static uint32_t crc_value = ~0U;
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/*
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* Uses the Trusted Entropy Source peripheral on Juno to return 8 bytes of
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* entropy. Returns 'true' when done successfully, 'false' otherwise.
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*/
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bool plat_get_entropy(uint64_t *out)
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{
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uint64_t ret;
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assert(out);
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assert(!check_uptr_overflow((uintptr_t)out, sizeof(*out)));
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if (!juno_trng_initialized) {
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/* Disable interrupt mode. */
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mmio_write_32(TRNG_BASE + TRNG_INTMASK, 0);
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/* Program TRNG to sample for `NSAMPLE_CLOCKS`. */
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mmio_write_32(TRNG_BASE + TRNG_CONFIG, NSAMPLE_CLOCKS);
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/* Abort any potentially pending sampling. */
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mmio_write_32(TRNG_BASE + TRNG_CONTROL, 2);
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/* Reset TRNG outputs. */
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mmio_write_32(TRNG_BASE + TRNG_STATUS, 1);
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juno_trng_initialized = true;
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}
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if (!output_valid()) {
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/* Start TRNG. */
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mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1);
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if (!output_valid())
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return false;
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}
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/* CRC each two 32-bit registers together, combine the pairs */
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crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 0));
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crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 4));
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ret = (uint64_t)crc_value << 32;
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crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 8));
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crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 12));
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*out = ret | crc_value;
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/* Acknowledge current cycle, clear output registers. */
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mmio_write_32(TRNG_BASE + TRNG_STATUS, 1);
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/* Trigger next TRNG cycle. */
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mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1);
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return true;
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}
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void plat_entropy_setup(void)
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{
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uint64_t dummy;
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plat_trng_uuid = _plat_trng_uuid;
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/* Initialise the entropy source and trigger RNG generation */
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plat_get_entropy(&dummy);
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}
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