67 lines
1.6 KiB
C
67 lines
1.6 KiB
C
/*
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* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <msm8916_mmap.h>
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#include "msm8916_pm.h"
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#define CPU_PWR_CTL 0x4
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#define APC_PWR_GATE_CTL 0x14
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#define CPU_PWR_CTL_CLAMP BIT_32(0)
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#define CPU_PWR_CTL_CORE_MEM_CLAMP BIT_32(1)
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#define CPU_PWR_CTL_L1_RST_DIS BIT_32(2)
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#define CPU_PWR_CTL_CORE_MEM_HS BIT_32(3)
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#define CPU_PWR_CTL_CORE_RST BIT_32(4)
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#define CPU_PWR_CTL_COREPOR_RST BIT_32(5)
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#define CPU_PWR_CTL_GATE_CLK BIT_32(6)
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#define CPU_PWR_CTL_CORE_PWRD_UP BIT_32(7)
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#define APC_PWR_GATE_CTL_GHDS_EN BIT_32(0)
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#define APC_PWR_GATE_CTL_GHDS_CNT(cnt) ((cnt) << 24)
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/* Boot a secondary CPU core for the first time. */
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void msm8916_cpu_boot(unsigned int core)
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{
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uintptr_t acs = APCS_ALIAS_ACS(core);
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uint32_t pwr_ctl;
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pwr_ctl = CPU_PWR_CTL_CLAMP | CPU_PWR_CTL_CORE_MEM_CLAMP |
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CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST;
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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mmio_write_32(acs + APC_PWR_GATE_CTL, APC_PWR_GATE_CTL_GHDS_EN |
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APC_PWR_GATE_CTL_GHDS_CNT(16));
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dsb();
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udelay(2);
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pwr_ctl &= ~CPU_PWR_CTL_CORE_MEM_CLAMP;
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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pwr_ctl |= CPU_PWR_CTL_CORE_MEM_HS;
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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udelay(2);
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pwr_ctl &= ~CPU_PWR_CTL_CLAMP;
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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udelay(2);
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pwr_ctl &= ~(CPU_PWR_CTL_CORE_RST | CPU_PWR_CTL_COREPOR_RST);
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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pwr_ctl |= CPU_PWR_CTL_CORE_PWRD_UP;
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mmio_write_32(acs + CPU_PWR_CTL, pwr_ctl);
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dsb();
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}
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