109 lines
4.4 KiB
C
109 lines
4.4 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#define PLAT_PRIMARY_CPU 0x0
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#define MT_GIC_BASE 0x0c000000
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#define PLAT_MT_CCI_BASE 0x0c500000
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#define MCUCFG_BASE 0x0c530000
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#define IO_PHYS 0x10000000
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/* Aggregate of all devices for MMU mapping */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x10000000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000)
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#define MTK_DEV_RNG1_SIZE 0x10000000
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#define MTK_DEV_RNG2_BASE 0x0c000000
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#define MTK_DEV_RNG2_SIZE 0x600000
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x01002000)
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#define UART1_BASE (IO_PHYS + 0x01003000)
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#define UART_BAUDRATE 115200
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_MHZ 13
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE MT_GIC_BASE
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#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLATFORM_STACK_SIZE 0x800
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
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#define SOC_CHIP_ID U(0x8192)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZRAM_BASE 0x54600000
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#define TZRAM_SIZE 0x00030000
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 16
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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