131 lines
4.7 KiB
C
131 lines
4.7 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <lib/utils_def.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
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******************************************************************************/
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#if !SEPARATE_CODE_AND_RODATA
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#error "SEPARATE_CODE_AND_RODATA should be set to 1"
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#endif
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/*
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* Platform binary types for linking
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*/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*
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* Platform binary types for linking
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*/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#ifdef IMAGE_BL31
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#define PLATFORM_STACK_SIZE U(0x400)
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#endif
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#define TEGRA_PRIMARY_CPU U(0x0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_MAX_CPUS_PER_CLUSTER)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + U(1))
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/*******************************************************************************
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* Platform console related constants
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******************************************************************************/
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#define TEGRA_CONSOLE_BAUDRATE U(115200)
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#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
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#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* Size of trusted dram */
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#define TZDRAM_SIZE U(0x00400000)
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#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE U(0x40000)
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#define BL31_BASE TZDRAM_BASE
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#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
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#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
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#define BL32_LIMIT TZDRAM_END
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/*******************************************************************************
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
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/*******************************************************************************
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* Dummy macros to compile io_storage support
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******************************************************************************/
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#define MAX_IO_DEVICES U(0)
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#define MAX_IO_HANDLES U(0)
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/*******************************************************************************
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* Platforms macros to support SDEI
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******************************************************************************/
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#define TEGRA_SDEI_SGI_PRIVATE U(8)
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/*******************************************************************************
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* Platform macros to support exception handling framework
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******************************************************************************/
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#define PLAT_PRI_BITS U(3)
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#define PLAT_RAS_PRI U(0x10)
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#define PLAT_SDEI_CRITICAL_PRI U(0x20)
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#define PLAT_SDEI_NORMAL_PRI U(0x30)
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#define PLAT_TEGRA_WDT_PRIO U(0x40)
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/*******************************************************************************
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* SDEI events
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******************************************************************************/
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/* SDEI dynamic private event numbers */
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#define TEGRA_SDEI_DP_EVENT_0 U(100)
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#define TEGRA_SDEI_DP_EVENT_1 U(101)
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#define TEGRA_SDEI_DP_EVENT_2 U(102)
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/* SDEI dynamic shared event numbers */
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#define TEGRA_SDEI_DS_EVENT_0 U(200)
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#define TEGRA_SDEI_DS_EVENT_1 U(201)
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#define TEGRA_SDEI_DS_EVENT_2 U(202)
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/* SDEI explicit events */
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#define TEGRA_SDEI_EP_EVENT_0 U(300)
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#define TEGRA_SDEI_EP_EVENT_1 U(301)
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#define TEGRA_SDEI_EP_EVENT_2 U(302)
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#define TEGRA_SDEI_EP_EVENT_3 U(303)
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#define TEGRA_SDEI_EP_EVENT_4 U(304)
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#define TEGRA_SDEI_EP_EVENT_5 U(305)
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#define TEGRA_SDEI_EP_EVENT_6 U(306)
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#define TEGRA_SDEI_EP_EVENT_7 U(307)
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#define TEGRA_SDEI_EP_EVENT_8 U(308)
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#define TEGRA_SDEI_EP_EVENT_9 U(309)
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#define TEGRA_SDEI_EP_EVENT_10 U(310)
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#define TEGRA_SDEI_EP_EVENT_11 U(311)
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#endif /* PLATFORM_DEF_H */
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