204 lines
6.3 KiB
C
204 lines
6.3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cassert.h>
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#include <common_def.h>
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#include <platform_def.h>
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#include <sys/types.h>
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#include <utils.h>
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#include <xlat_tables_v2.h>
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#include "../xlat_tables_private.h"
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
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# define IMAGE_EL 3
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#else
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# define IMAGE_EL 1
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#endif
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static unsigned long long tcr_ps_bits;
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static unsigned long long calc_physical_addr_size_bits(
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unsigned long long max_addr)
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{
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/* Physical address can't exceed 48 bits */
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assert((max_addr & ADDR_MASK_48_TO_63) == 0);
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/* 48 bits address */
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if (max_addr & ADDR_MASK_44_TO_47)
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return TCR_PS_BITS_256TB;
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/* 44 bits address */
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if (max_addr & ADDR_MASK_42_TO_43)
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return TCR_PS_BITS_16TB;
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/* 42 bits address */
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if (max_addr & ADDR_MASK_40_TO_41)
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return TCR_PS_BITS_4TB;
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/* 40 bits address */
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if (max_addr & ADDR_MASK_36_TO_39)
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return TCR_PS_BITS_1TB;
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/* 36 bits address */
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if (max_addr & ADDR_MASK_32_TO_35)
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return TCR_PS_BITS_64GB;
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return TCR_PS_BITS_4GB;
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}
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#if DEBUG
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/* Physical Address ranges supported in the AArch64 Memory Model */
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static const unsigned int pa_range_bits_arr[] = {
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PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
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PARANGE_0101
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};
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unsigned long long xlat_arch_get_max_supported_pa(void)
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{
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u_register_t pa_range = read_id_aa64mmfr0_el1() &
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ID_AA64MMFR0_EL1_PARANGE_MASK;
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/* All other values are reserved */
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assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
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return (1ull << pa_range_bits_arr[pa_range]) - 1ull;
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}
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#endif /* DEBUG*/
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int is_mmu_enabled(void)
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{
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#if IMAGE_EL == 1
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assert(IS_IN_EL(1));
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return (read_sctlr_el1() & SCTLR_M_BIT) != 0;
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#elif IMAGE_EL == 3
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assert(IS_IN_EL(3));
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return (read_sctlr_el3() & SCTLR_M_BIT) != 0;
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#endif
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}
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void init_xlat_tables_arch(unsigned long long max_pa)
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{
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assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <=
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xlat_arch_get_max_supported_pa());
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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}
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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*
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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void enable_mmu_internal_el##_el(unsigned int flags, \
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uint64_t *base_table) \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr; \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
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\
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
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ATTR_NON_CACHEABLE_INDEX); \
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write_mair_el##_el(mair); \
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\
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/* Set TCR bits as well. */ \
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/* Inner & outer WBWA & shareable. */ \
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/* Set T0SZ to (64 - width of virtual address space) */ \
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
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TCR_RGN_INNER_WBA | \
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) base_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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/* into memory, the TLB invalidation is complete, */ \
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/* and translation register writes are committed */ \
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/* before enabling the MMU */ \
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dsb(); \
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isb(); \
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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\
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if (flags & DISABLE_DCACHE) \
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sctlr &= ~SCTLR_C_BIT; \
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else \
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sctlr |= SCTLR_C_BIT; \
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\
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write_sctlr_el##_el(sctlr); \
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\
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/* Ensure the MMU enable takes effect immediately */ \
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isb(); \
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}
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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#if IMAGE_EL == 1
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DEFINE_ENABLE_MMU_EL(1,
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(tcr_ps_bits << TCR_EL1_IPS_SHIFT),
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tlbivmalle1)
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#elif IMAGE_EL == 3
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DEFINE_ENABLE_MMU_EL(3,
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TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
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tlbialle3)
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#endif
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void enable_mmu_arch(unsigned int flags, uint64_t *base_table)
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{
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#if IMAGE_EL == 1
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assert(IS_IN_EL(1));
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enable_mmu_internal_el1(flags, base_table);
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#elif IMAGE_EL == 3
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assert(IS_IN_EL(3));
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enable_mmu_internal_el3(flags, base_table);
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#endif
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}
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