Jiafei Pan 7d173fc594 Add support for BL2 in XIP memory ... In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This patch enable this use-case with a new build option, BL2_IN_XIP_MEM. For now, this option is only supported when BL2_AT_EL3 is 1. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>		2018-04-07 10:12:21 +08:00
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aarch32	bl2-el3: Fix bl32 lr_svc used for bl33 entry address	2018-03-05 17:34:25 +01:00
aarch64	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
bl2.ld.S	Add comments about mismatched TCR_ELx and xlat tables	2018-02-27 09:55:01 +00:00
bl2.mk	Add image_id to bl1_plat_handle_post/pre_image_load()	2018-02-26 16:29:29 +00:00
bl2_el3.ld.S	Add support for BL2 in XIP memory	2018-04-07 10:12:21 +08:00
bl2_image_load.c	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
bl2_image_load_v2.c	Fix MISRA rule 8.4 Part 1	2018-02-28 17:19:55 +00:00
bl2_main.c	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
bl2_private.h	Add support for BL2 in XIP memory	2018-04-07 10:12:21 +08:00