183 lines
5.5 KiB
C
183 lines
5.5 KiB
C
/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_FCS_H
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#define SOCFPGA_FCS_H
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/* FCS Definitions */
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#define FCS_RANDOM_WORD_SIZE 8U
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#define FCS_PROV_DATA_WORD_SIZE 44U
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#define FCS_SHA384_WORD_SIZE 12U
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#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
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#define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U
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#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
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#define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U)
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#define FCS_RANDOM_EXT_OFFSET 3
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#define FCS_MODE_DECRYPT 0x0
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#define FCS_MODE_ENCRYPT 0x1
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#define FCS_ENCRYPTION_DATA_0 0x10100
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#define FCS_DECRYPTION_DATA_0 0x10102
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#define FCS_OWNER_ID_OFFSET 0xC
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#define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4
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#define PSGSIGMA_SESSION_ID_ONE 0x1
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#define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF
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#define RESERVED_AS_ZERO 0x0
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/* FCS Single cert */
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#define FCS_BIG_CNTR_SEL 0x1
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#define FCS_SVN_CNTR_0_SEL 0x2
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#define FCS_SVN_CNTR_1_SEL 0x3
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#define FCS_SVN_CNTR_2_SEL 0x4
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#define FCS_SVN_CNTR_3_SEL 0x5
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#define FCS_BIG_CNTR_VAL_MAX 495U
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#define FCS_SVN_CNTR_VAL_MAX 64U
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/* FCS Attestation Cert Request Parameter */
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#define FCS_ALIAS_CERT 0x01
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#define FCS_DEV_ID_SELF_SIGN_CERT 0x02
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#define FCS_DEV_ID_ENROLL_CERT 0x04
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#define FCS_ENROLL_SELF_SIGN_CERT 0x08
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#define FCS_PLAT_KEY_CERT 0x10
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/* FCS Crypto Service */
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#define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U
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#define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U
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#define FCS_CS_KEY_RESP_STATUS_MASK 0xFF
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#define FCS_CS_KEY_RESP_STATUS_OFFSET 16U
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#define FCS_CS_FIELD_SIZE_MASK 0xFFFF
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#define FCS_CS_FIELD_FLAG_OFFSET 24
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#define FCS_CS_FIELD_FLAG_INIT BIT(0)
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#define FCS_CS_FIELD_FLAG_UPDATE BIT(1)
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#define FCS_CS_FIELD_FLAG_FINALIZE BIT(2)
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#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
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#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
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#define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U
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/* FCS Payload Structure */
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typedef struct fcs_rng_payload_t {
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uint32_t session_id;
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uint32_t context_id;
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uint32_t crypto_header;
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uint32_t size;
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} fcs_rng_payload;
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typedef struct fcs_encrypt_payload_t {
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uint32_t first_word;
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uint32_t src_addr;
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uint32_t src_size;
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uint32_t dst_addr;
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uint32_t dst_size;
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} fcs_encrypt_payload;
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typedef struct fcs_decrypt_payload_t {
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uint32_t first_word;
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uint32_t owner_id[2];
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uint32_t src_addr;
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uint32_t src_size;
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uint32_t dst_addr;
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uint32_t dst_size;
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} fcs_decrypt_payload;
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typedef struct psgsigma_teardown_msg_t {
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uint32_t reserved_word;
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uint32_t magic_word;
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uint32_t session_id;
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} psgsigma_teardown_msg;
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typedef struct fcs_cntr_set_preauth_payload_t {
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uint32_t first_word;
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uint32_t counter_value;
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} fcs_cntr_set_preauth_payload;
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typedef struct fcs_cs_key_payload_t {
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uint32_t session_id;
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uint32_t reserved0;
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uint32_t reserved1;
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uint32_t key_id;
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} fcs_cs_key_payload;
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typedef struct fcs_crypto_service_data_t {
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uint32_t session_id;
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uint32_t context_id;
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uint32_t key_id;
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uint32_t crypto_param_size;
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uint64_t crypto_param;
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} fcs_crypto_service_data;
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/* Functions Definitions */
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uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error);
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int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
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uint32_t size, uint32_t *send_id);
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uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
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uint32_t *send_id);
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uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
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uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
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int32_t counter_value,
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uint32_t test_bit,
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uint32_t *mbox_error);
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uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
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uint32_t dst_addr, uint32_t dst_size,
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uint32_t *send_id);
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uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
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uint32_t dst_addr, uint32_t dst_size,
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uint32_t *send_id);
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int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
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int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
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int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size,
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uint64_t dst_addr, uint32_t *dst_size,
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uint32_t *mbox_error);
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int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size,
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uint64_t dst_addr, uint32_t *dst_size,
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uint32_t *mbox_error);
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uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error);
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int intel_fcs_create_cert_on_reload(uint32_t cert_request,
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uint32_t *mbox_error);
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int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
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uint32_t *dst_size, uint32_t *mbox_error);
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int intel_fcs_open_crypto_service_session(uint32_t *session_id,
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uint32_t *mbox_error);
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int intel_fcs_close_crypto_service_session(uint32_t session_id,
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uint32_t *mbox_error);
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int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size,
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uint32_t *mbox_error);
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int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id,
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uint64_t dst_addr, uint32_t *dst_size,
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uint32_t *mbox_error);
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int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id,
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uint32_t *mbox_error);
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int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id,
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uint64_t dst_addr, uint32_t *dst_size,
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uint32_t *mbox_error);
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int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
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uint32_t key_id, uint32_t param_size,
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uint64_t param_data, uint32_t *mbox_error);
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int intel_fcs_get_digest_finalize(uint32_t session_id, uint32_t context_id,
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uint32_t src_addr, uint32_t src_size,
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uint64_t dst_addr, uint32_t *dst_size,
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uint32_t *mbox_error);
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#endif /* SOCFPGA_FCS_H */
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