64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/trbe.h>
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static void tsb_csync(void)
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{
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/*
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* The assembler does not yet understand the tsb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #18");
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}
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static bool trbe_supported(void)
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{
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uint64_t features;
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features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT;
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return ((features & ID_AA64DFR0_TRACEBUFFER_MASK) ==
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ID_AA64DFR0_TRACEBUFFER_SUPPORTED);
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}
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void trbe_enable(void)
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{
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uint64_t val;
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if (trbe_supported()) {
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/*
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* MDCR_EL3.NSTB = 0b11
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* Allow access of trace buffer control registers from NS-EL1
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* and NS-EL2, tracing is prohibited in Secure and Realm state
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* (if implemented).
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*/
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val = read_mdcr_el3();
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val |= MDCR_NSTB(MDCR_NSTB_EL1);
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write_mdcr_el3(val);
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}
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}
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static void *trbe_drain_trace_buffers_hook(const void *arg __unused)
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{
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if (trbe_supported()) {
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/*
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* Before switching from normal world to secure world
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* the trace buffers need to be drained out to memory. This is
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* required to avoid an invalid memory access when TTBR is switched
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* for entry to S-EL1.
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*/
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tsb_csync();
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dsbnsh();
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}
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, trbe_drain_trace_buffers_hook);
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