92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <console.h>
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#include <generic_delay_timer.h>
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#include <plat_arm.h>
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#include <platform.h>
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#pragma weak bl2_el3_early_platform_setup
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#pragma weak bl2_el3_plat_arch_setup
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#pragma weak bl2_el3_plat_prepare_exit
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static meminfo_t bl2_el3_tzram_layout;
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/*
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* Perform arm specific early platform setup. At this moment we only initialize
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* the console and the memory layout.
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*/
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void arm_bl2_el3_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
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ARM_CONSOLE_BAUDRATE);
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/*
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* Allow BL2 to see the whole Trusted RAM. This is determined
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* statically since we cannot rely on BL1 passing this information
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* in the BL2_AT_EL3 case.
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*/
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bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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}
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void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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arm_bl2_el3_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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*/
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plat_arm_interconnect_enter_coherency();
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generic_delay_timer_init();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only initializes the mmu in a quick and dirty way.
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******************************************************************************/
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void arm_bl2_el3_plat_arch_setup(void)
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{
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arm_setup_page_tables(bl2_el3_tzram_layout.total_base,
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bl2_el3_tzram_layout.total_size,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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#ifdef AARCH32
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enable_mmu_secure(0);
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#else
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enable_mmu_el3(0);
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#endif
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}
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void bl2_el3_plat_arch_setup(void)
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{
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arm_bl2_el3_plat_arch_setup();
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}
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void bl2_el3_plat_prepare_exit(void)
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{
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}
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