101 lines
2.8 KiB
ArmAsm
101 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <smcc_helpers.h>
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#include <smcc_macros.S>
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.globl bl1_vector_table
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.globl bl1_entrypoint
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/* -----------------------------------------------------
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* Setup the vector table to support SVC & MON mode.
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* -----------------------------------------------------
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*/
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vector_base bl1_vector_table
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b bl1_entrypoint
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b report_exception /* Undef */
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b bl1_aarch32_smc_handler /* SMC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_vector_table
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/* -----------------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* -----------------------------------------------------
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*/
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bl bl1_early_platform_setup
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bl bl1_plat_arch_setup
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/* -----------------------------------------------------
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* Jump to main function.
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* -----------------------------------------------------
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*/
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bl bl1_main
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/* -----------------------------------------------------
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* Jump to next image.
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* -----------------------------------------------------
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*/
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/*
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* MMU needs to be disabled because both BL1 and BL2 execute
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* in PL1, and therefore share the same address space.
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* BL2 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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/* Get the cpu_context for next BL image */
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bl cm_get_next_context
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/* Restore the SCR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR]
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stcopr r2, SCR
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isb
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/*
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* Get the smc_context for next BL image,
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* program the gp/system registers and exit
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* secure monitor mode
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*/
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bl smc_get_next_ctx
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smcc_restore_gp_mode_regs
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eret
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endfunc bl1_entrypoint
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